Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24208804	5777	0	0
EscTimeoutStoppedByClReset_A	24208215	3442885	0	0
EscTimeoutTriggersReset_A	5178157	316	0	0
RomAllowActiveState_A	24208215	59910	0	0
RomAllowCheckGoodState_A	24208215	59965	0	0
RomBlockActiveState_A	24208215	31792	0	0
RomBlockCheckGoodState_A	24208215	443728	0	0
RomIntgChkDisFalse_A	24208215	23450724	0	0
RomIntgChkDisTrue_A	24208215	233923	0	0
RstreqChkEsctimeout_A	24208215	4268	0	0
RstreqChkFsmterm_A	24208215	140	0	0
RstreqChkGlbesc_A	24208215	4268	0	0
RstreqChkMainpd_A	24208215	995407	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208804	5777	0	0
T10	15207	47	0	0
T11	804	8	0	0
T12	0	36	0	0
T13	6041	0	0	0
T14	180032	0	0	0
T24	18084	0	0	0
T37	8533	0	0	0
T40	1158	0	0	0
T42	1248	0	0	0
T43	3255	0	0	0
T72	2353	0	0	0
T99	0	10	0	0
T100	0	217	0	0
T152	0	8	0	0
T153	0	7	0	0
T154	0	32	0	0
T155	0	29	0	0
T156	0	55	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	3442885	0	0
T1	4464	1025	0	0
T2	8449	260	0	0
T3	5945	853	0	0
T4	2869	59	0	0
T5	6932	608	0	0
T6	3983	702	0	0
T7	1995	238	0	0
T8	1088	108	0	0
T9	24023	3624	0	0
T10	15206	19	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5178157	316	0	0
T10	423	2	0	0
T11	261	5	0	0
T12	0	3	0	0
T13	633	0	0	0
T14	18148	0	0	0
T24	7315	0	0	0
T37	821	0	0	0
T40	397	0	0	0
T42	412	0	0	0
T43	304	0	0	0
T72	207	0	0	0
T99	0	4	0	0
T100	0	3	0	0
T152	0	4	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	2	0	0
T157	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	59910	0	0
T1	4464	8	0	0
T2	8449	13	0	0
T3	5945	26	0	0
T4	2869	5	0	0
T5	6932	18	0	0
T6	3983	13	0	0
T7	1995	5	0	0
T8	1088	2	0	0
T9	24023	89	0	0
T10	15206	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	59965	0	0
T1	4464	8	0	0
T2	8449	14	0	0
T3	5945	26	0	0
T4	2869	5	0	0
T5	6932	18	0	0
T6	3983	13	0	0
T7	1995	5	0	0
T8	1088	2	0	0
T9	24023	89	0	0
T10	15206	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	31792	0	0
T12	2472	0	0	0
T25	4946	626	0	0
T29	0	12	0	0
T34	0	773	0	0
T36	0	1	0	0
T41	1539	0	0	0
T45	16001	6	0	0
T46	0	594	0	0
T58	8036	0	0	0
T73	7269	0	0	0
T75	1712	0	0	0
T76	1833	0	0	0
T94	1207	0	0	0
T105	1884	0	0	0
T158	0	112	0	0
T159	0	12	0	0
T160	0	26	0	0
T161	0	1509	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	443728	0	0
T9	24023	1313	0	0
T10	15206	0	0	0
T11	803	0	0	0
T13	6040	0	0	0
T14	180031	390	0	0
T16	0	4883	0	0
T23	0	2421	0	0
T24	18083	1333	0	0
T25	0	1136	0	0
T37	8532	0	0	0
T40	1157	0	0	0
T42	1247	0	0	0
T43	3254	0	0	0
T45	0	797	0	0
T73	0	437	0	0
T137	0	206	0	0
T147	0	253	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	23450724	0	0
T1	4464	4365	0	0
T2	8449	7363	0	0
T3	5945	5872	0	0
T4	2869	2513	0	0
T5	6932	6871	0	0
T6	3983	3886	0	0
T7	1995	1925	0	0
T8	1088	1007	0	0
T9	24023	7410	0	0
T10	15206	15150	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	233923	0	0
T9	24023	16520	0	0
T10	15206	0	0	0
T11	803	0	0	0
T13	6040	0	0	0
T14	180031	0	0	0
T24	18083	300	0	0
T25	0	1004	0	0
T29	0	674	0	0
T34	0	1341	0	0
T37	8532	0	0	0
T40	1157	0	0	0
T42	1247	0	0	0
T43	3254	0	0	0
T158	0	1063	0	0
T159	0	391	0	0
T160	0	342	0	0
T161	0	1594	0	0
T162	0	28611	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	4268	0	0
T2	8449	8	0	0
T3	5945	8	0	0
T4	2869	0	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	0	0	0
T10	15206	1	0	0
T11	803	1	0	0
T13	0	5	0	0
T14	0	43	0	0
T37	0	6	0	0
T38	0	8	0	0
T39	0	8	0	0
T40	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	140	0	0
T20	9275	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	2508	0	0	0
T29	17092	0	0	0
T30	8512	0	0	0
T31	1467	0	0	0
T32	17220	0	0	0
T33	326813	0	0	0
T34	4502	0	0	0
T35	1335	0	0	0
T36	18266	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	4268	0	0
T2	8449	8	0	0
T3	5945	8	0	0
T4	2869	0	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	0	0	0
T10	15206	1	0	0
T11	803	1	0	0
T13	0	5	0	0
T14	0	43	0	0
T37	0	6	0	0
T38	0	8	0	0
T39	0	8	0	0
T40	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	995407	0	0
T2	8449	174	0	0
T3	5945	792	0	0
T4	2869	0	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	1449	0	0
T10	15206	0	0	0
T11	803	0	0	0
T13	0	87	0	0
T14	0	5320	0	0
T16	0	9872	0	0
T24	0	994	0	0
T37	0	203	0	0
T38	0	923	0	0
T39	0	116	0	0