Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	537882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207566

1

T2

1

T3

83

T4

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	388102	1			T1	1		T2	1		T3	146
values[0x0]	178270	1			T3	71		T4	22		T6	219
values[0x1]	179076	1			T3	69		T4	34		T6	233

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	426152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

319296

1

T1

1

T2

1

T3

122

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3473	1			T8	2		T14	16		T20	13
valid_sources[0x01]	2584	1			T8	2		T14	7		T20	29
valid_sources[0x02]	4618	1			T3	6		T14	10		T22	2
valid_sources[0x03]	2555	1			T4	153		T14	7		T20	13
valid_sources[0x04]	2536	1			T8	1		T9	4		T14	9
valid_sources[0x05]	3324	1			T3	9		T14	5		T25	1
valid_sources[0x06]	3147	1			T14	6		T20	2		T25	1
valid_sources[0x07]	2625	1			T14	7		T25	2		T41	1
valid_sources[0x08]	2579	1			T3	4		T8	2		T14	12
valid_sources[0x09]	2464	1			T9	7		T14	4		T37	2
valid_sources[0x0a]	3160	1			T14	5		T20	565		T37	3
valid_sources[0x0b]	3132	1			T8	2		T9	15		T14	4
valid_sources[0x0c]	2641	1			T8	1		T14	11		T25	2
valid_sources[0x0d]	2901	1			T14	7		T25	1		T37	6
valid_sources[0x0e]	4476	1			T14	12		T20	27		T43	2
valid_sources[0x0f]	3166	1			T3	9		T9	1		T14	2
valid_sources[0x10]	2894	1			T14	8		T20	14		T37	2
valid_sources[0x11]	2531	1			T14	11		T20	23		T25	1
valid_sources[0x12]	3286	1			T3	3		T14	1		T37	3
valid_sources[0x13]	2620	1			T3	4		T14	12		T41	1
valid_sources[0x14]	3446	1			T3	1		T14	9		T37	3
valid_sources[0x15]	2656	1			T9	13		T14	14		T20	15
valid_sources[0x16]	2548	1			T8	1		T25	1		T41	1
valid_sources[0x17]	2768	1			T3	3		T8	1		T14	12
valid_sources[0x18]	3337	1			T14	9		T20	24		T25	2
valid_sources[0x19]	2513	1			T3	1		T8	1		T14	16
valid_sources[0x1a]	3004	1			T14	7		T20	13		T41	2
valid_sources[0x1b]	2598	1			T14	8		T20	5		T37	6
valid_sources[0x1c]	2926	1			T14	11		T20	15		T22	1
valid_sources[0x1d]	4088	1			T8	1		T14	9		T20	17
valid_sources[0x1e]	2716	1			T9	8		T14	7		T41	1
valid_sources[0x1f]	2471	1			T14	8		T41	2		T43	1
valid_sources[0x20]	3108	1			T14	6		T37	4		T44	2
valid_sources[0x21]	3022	1			T14	6		T20	3		T25	1
valid_sources[0x22]	2578	1			T8	1		T14	7		T25	1
valid_sources[0x23]	2848	1			T3	6		T14	9		T25	1
valid_sources[0x24]	2991	1			T3	1		T9	1		T14	18
valid_sources[0x25]	3950	1			T3	2		T14	11		T20	14
valid_sources[0x26]	2468	1			T14	14		T20	13		T41	1
valid_sources[0x27]	2975	1			T14	14		T20	375		T25	1
valid_sources[0x28]	2259	1			T14	8		T37	3		T63	1
valid_sources[0x29]	2642	1			T7	1		T8	1		T14	7
valid_sources[0x2a]	2446	1			T14	6		T43	1		T37	2
valid_sources[0x2b]	2471	1			T8	1		T9	5		T14	5
valid_sources[0x2c]	5041	1			T14	15		T22	1		T41	1
valid_sources[0x2d]	3581	1			T3	4		T14	7		T37	1
valid_sources[0x2e]	2714	1			T14	11		T43	1		T37	5
valid_sources[0x2f]	2800	1			T3	2		T14	13		T20	12
valid_sources[0x30]	2532	1			T14	8		T25	2		T43	1
valid_sources[0x31]	2826	1			T14	10		T43	2		T37	4
valid_sources[0x32]	2370	1			T9	2		T14	5		T20	14
valid_sources[0x33]	3207	1			T8	1		T14	9		T25	2
valid_sources[0x34]	2605	1			T8	1		T14	6		T25	1
valid_sources[0x35]	2655	1			T8	1		T9	2		T14	2
valid_sources[0x36]	2718	1			T1	1		T14	8		T20	13
valid_sources[0x37]	2896	1			T8	1		T14	11		T25	3
valid_sources[0x38]	2471	1			T3	5		T14	7		T20	2
valid_sources[0x39]	2532	1			T14	5		T25	1		T41	2
valid_sources[0x3a]	3770	1			T3	2		T14	1		T20	5
valid_sources[0x3b]	3295	1			T14	10		T22	1		T41	1
valid_sources[0x3c]	2486	1			T3	3		T8	1		T14	9
valid_sources[0x3d]	2550	1			T3	5		T14	9		T20	26
valid_sources[0x3e]	2673	1			T3	1		T4	5		T14	12
valid_sources[0x3f]	2712	1			T3	4		T8	1		T14	10
valid_sources[0x40]	2647	1			T3	1		T14	9		T41	1
valid_sources[0x41]	2845	1			T3	2		T8	1		T14	10
valid_sources[0x42]	2671	1			T14	11		T20	14		T41	1
valid_sources[0x43]	3062	1			T14	11		T41	1		T37	6
valid_sources[0x44]	4374	1			T3	1		T14	8		T20	1859
valid_sources[0x45]	2471	1			T3	3		T14	12		T37	7
valid_sources[0x46]	2579	1			T14	8		T41	2		T37	7
valid_sources[0x47]	3491	1			T3	4		T14	3		T20	25
valid_sources[0x48]	2432	1			T14	13		T20	13		T25	1
valid_sources[0x49]	2503	1			T8	1		T14	3		T20	33
valid_sources[0x4a]	3010	1			T14	7		T20	29		T41	2
valid_sources[0x4b]	3355	1			T14	6		T37	3		T80	2
valid_sources[0x4c]	2614	1			T14	9		T37	6		T39	8
valid_sources[0x4d]	2657	1			T14	4		T41	1		T43	1
valid_sources[0x4e]	2510	1			T14	13		T37	5		T21	33
valid_sources[0x4f]	2499	1			T3	1		T9	5		T14	13
valid_sources[0x50]	3559	1			T14	4		T25	2		T41	1
valid_sources[0x51]	4702	1			T14	10		T20	2110		T41	1
valid_sources[0x52]	2625	1			T14	10		T20	7		T22	2
valid_sources[0x53]	2683	1			T14	16		T25	1		T41	1
valid_sources[0x54]	2491	1			T3	4		T14	7		T22	1
valid_sources[0x55]	2583	1			T3	3		T8	4		T9	3
valid_sources[0x56]	2415	1			T14	16		T20	13		T41	2
valid_sources[0x57]	2576	1			T14	4		T41	1		T37	6
valid_sources[0x58]	3043	1			T8	1		T14	21		T25	2
valid_sources[0x59]	3325	1			T3	11		T14	5		T20	13
valid_sources[0x5a]	3258	1			T8	2		T14	10		T22	1
valid_sources[0x5b]	2509	1			T14	11		T25	2		T43	6
valid_sources[0x5c]	2701	1			T14	11		T37	3		T40	1
valid_sources[0x5d]	2499	1			T8	1		T14	6		T43	4
valid_sources[0x5e]	3300	1			T2	1		T3	3		T14	12
valid_sources[0x5f]	2752	1			T14	6		T20	13		T25	1
valid_sources[0x60]	2877	1			T14	3		T20	14		T22	1
valid_sources[0x61]	3354	1			T8	1		T14	13		T41	2
valid_sources[0x62]	2951	1			T3	11		T8	1		T14	8
valid_sources[0x63]	2898	1			T14	6		T20	3		T25	3
valid_sources[0x64]	3184	1			T3	5		T8	2		T14	8
valid_sources[0x65]	2864	1			T14	7		T20	17		T41	1
valid_sources[0x66]	2560	1			T3	1		T14	9		T22	1
valid_sources[0x67]	4048	1			T9	9		T14	10		T20	13
valid_sources[0x68]	2586	1			T14	8		T43	1		T37	7
valid_sources[0x69]	2885	1			T8	1		T14	14		T37	7
valid_sources[0x6a]	2781	1			T14	2		T20	13		T25	1
valid_sources[0x6b]	2607	1			T14	9		T20	38		T22	1
valid_sources[0x6c]	2570	1			T9	3		T14	7		T22	2
valid_sources[0x6d]	2429	1			T14	7		T20	35		T41	2
valid_sources[0x6e]	3220	1			T5	1		T14	5		T20	4
valid_sources[0x6f]	3027	1			T3	4		T14	6		T20	14
valid_sources[0x70]	2480	1			T3	16		T8	4		T9	10
valid_sources[0x71]	3419	1			T14	12		T25	2		T41	3
valid_sources[0x72]	3146	1			T14	10		T20	14		T41	2
valid_sources[0x73]	2596	1			T9	3		T14	3		T20	15
valid_sources[0x74]	3075	1			T14	7		T41	1		T43	2
valid_sources[0x75]	4995	1			T4	5		T14	9		T25	2
valid_sources[0x76]	2627	1			T4	5		T14	5		T20	14
valid_sources[0x77]	2386	1			T14	10		T22	1		T41	1
valid_sources[0x78]	2607	1			T3	3		T8	1		T14	9
valid_sources[0x79]	3550	1			T14	5		T25	1		T41	2
valid_sources[0x7a]	2620	1			T3	12		T9	1		T14	6
valid_sources[0x7b]	2606	1			T14	7		T20	29		T41	1
valid_sources[0x7c]	2436	1			T14	5		T20	13		T22	2
valid_sources[0x7d]	2925	1			T14	7		T20	156		T37	6
valid_sources[0x7e]	2426	1			T14	7		T37	2		T63	2
valid_sources[0x7f]	2807	1			T3	2		T8	1		T14	13
valid_sources[0x80]	2569	1			T3	1		T14	9		T43	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

104822

1

T2

1

T3

48

T4

63

values[0x0]

all_enables

biggest_size

66500

1

T3

25

T4

7

T6

78

values[0x1]

all_enables

biggest_size

36244

1

T3

10

T4

5

T6

35