SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34893 | 1 | T6 | 425 | T23 | 325 | T24 | 296 | ||||
others[1] | 34897 | 1 | T6 | 376 | T23 | 279 | T24 | 299 | ||||
others[2] | 35201 | 1 | T6 | 407 | T23 | 292 | T24 | 313 | ||||
others[3] | 58426 | 1 | T6 | 662 | T23 | 506 | T24 | 493 | ||||
false | 19809 | 1 | T6 | 50 | T14 | 4 | T20 | 326 | ||||
true | 29995 | 1 | T1 | 5 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35068 | 1 | T6 | 392 | T23 | 318 | T24 | 313 | ||||
others[1] | 35136 | 1 | T6 | 404 | T23 | 284 | T24 | 273 | ||||
others[2] | 34975 | 1 | T6 | 394 | T23 | 304 | T24 | 297 | ||||
others[3] | 58121 | 1 | T6 | 681 | T23 | 483 | T24 | 519 | ||||
false | 12504 | 1 | T6 | 50 | T14 | 2 | T20 | 163 | ||||
true | 22757 | 1 | T1 | 5 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 686 | 1 | T20 | 5 | T63 | 3 | T39 | 2 | ||||
others[1] | 730 | 1 | T20 | 5 | T37 | 2 | T63 | 7 | ||||
others[2] | 733 | 1 | T14 | 1 | T20 | 4 | T25 | 1 | ||||
others[3] | 1133 | 1 | T14 | 2 | T20 | 9 | T22 | 3 | ||||
false | 13885 | 1 | T1 | 5 | T2 | 2 | T3 | 1 | ||||
true | 4062 | 1 | T14 | 4 | T20 | 50 | T22 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |