Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25588046	16162	0	0
intr_enable_rd_A	25588046	43940	0	0
reset_en_rd_A	25588046	1952	0	0
reset_en_regwen_rd_A	25588046	1963	0	0
wake_info_capture_dis_rd_A	25588046	1792	0	0
wakeup_en_rd_A	25588046	2996	0	0
wakeup_en_regwen_rd_A	25588046	2077	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	16162	0	0
T14	53391	66	0	0
T20	629218	22	0	0
T21	0	25	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T52	0	21	0	0
T53	0	3	0	0
T55	0	78	0	0
T116	0	18	0	0
T117	0	3	0	0
T118	0	3	0	0
T119	0	36	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	43940	0	0
T20	629218	2557	0	0
T22	1965	1	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T28	0	496	0	0
T33	0	3	0	0
T37	65135	228	0	0
T38	2879	10	0	0
T41	9332	0	0	0
T43	5399	34	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T63	0	72	0	0
T81	0	17	0	0
T82	0	11	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	1952	0	0
T20	629218	20	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T57	0	48	0	0
T71	0	2	0	0
T79	0	25	0	0
T98	0	11	0	0
T120	0	3	0	0
T121	0	19	0	0
T122	0	12	0	0
T123	0	3	0	0
T124	0	1	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	1963	0	0
T20	629218	8	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T74	0	4	0	0
T79	0	16	0	0
T84	0	5	0	0
T120	0	4	0	0
T121	0	20	0	0
T123	0	15	0	0
T125	0	1	0	0
T126	0	3	0	0
T127	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	1792	0	0
T20	629218	6	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T74	0	4	0	0
T79	0	15	0	0
T84	0	1	0	0
T120	0	5	0	0
T121	0	16	0	0
T122	0	4	0	0
T123	0	9	0	0
T125	0	3	0	0
T128	0	6	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	2996	0	0
T20	629218	10	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T74	0	7	0	0
T79	0	10	0	0
T120	0	7	0	0
T121	0	19	0	0
T122	0	3	0	0
T123	0	6	0	0
T125	0	3	0	0
T126	0	2	0	0
T128	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25588046	2077	0	0
T20	629218	14	0	0
T22	1965	0	0	0
T23	18513	0	0	0
T25	1635	0	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T71	0	4	0	0
T79	0	17	0	0
T120	0	2	0	0
T121	0	5	0	0
T122	0	2	0	0
T123	0	8	0	0
T125	0	10	0	0
T126	0	6	0	0
T129	0	5	0	0