SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 100.00 | 83.87 | 99.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 100.00 | 83.87 | 99.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1908 | 1908 | 0 | 0 |
OutputsKnown_A | 49971614 | 48897654 | 0 | 0 |
gen_flops.OutputDelay_A | 49971614 | 48854432 | 0 | 5724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1908 | 1908 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T10 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49971614 | 48897654 | 0 | 0 |
T1 | 2692 | 1970 | 0 | 0 |
T2 | 3966 | 3678 | 0 | 0 |
T3 | 9786 | 9620 | 0 | 0 |
T4 | 4382 | 4272 | 0 | 0 |
T5 | 6964 | 6070 | 0 | 0 |
T6 | 45762 | 45458 | 0 | 0 |
T7 | 3392 | 2614 | 0 | 0 |
T8 | 3390 | 3254 | 0 | 0 |
T9 | 6506 | 6312 | 0 | 0 |
T10 | 6502 | 5752 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49971614 | 48854432 | 0 | 5724 |
T1 | 2692 | 1940 | 0 | 6 |
T2 | 3966 | 3666 | 0 | 6 |
T3 | 9786 | 9614 | 0 | 6 |
T4 | 4382 | 4266 | 0 | 6 |
T5 | 6964 | 6034 | 0 | 6 |
T6 | 45762 | 45446 | 0 | 6 |
T7 | 3392 | 2584 | 0 | 6 |
T8 | 3390 | 3248 | 0 | 6 |
T9 | 6506 | 6306 | 0 | 6 |
T10 | 6502 | 5722 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 954 | 954 | 0 | 0 |
OutputsKnown_A | 24985807 | 24448827 | 0 | 0 |
gen_flops.OutputDelay_A | 24985807 | 24427216 | 0 | 2862 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 954 | 954 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24985807 | 24448827 | 0 | 0 |
T1 | 1346 | 985 | 0 | 0 |
T2 | 1983 | 1839 | 0 | 0 |
T3 | 4893 | 4810 | 0 | 0 |
T4 | 2191 | 2136 | 0 | 0 |
T5 | 3482 | 3035 | 0 | 0 |
T6 | 22881 | 22729 | 0 | 0 |
T7 | 1696 | 1307 | 0 | 0 |
T8 | 1695 | 1627 | 0 | 0 |
T9 | 3253 | 3156 | 0 | 0 |
T10 | 3251 | 2876 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24985807 | 24427216 | 0 | 2862 |
T1 | 1346 | 970 | 0 | 3 |
T2 | 1983 | 1833 | 0 | 3 |
T3 | 4893 | 4807 | 0 | 3 |
T4 | 2191 | 2133 | 0 | 3 |
T5 | 3482 | 3017 | 0 | 3 |
T6 | 22881 | 22723 | 0 | 3 |
T7 | 1696 | 1292 | 0 | 3 |
T8 | 1695 | 1624 | 0 | 3 |
T9 | 3253 | 3153 | 0 | 3 |
T10 | 3251 | 2861 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 954 | 954 | 0 | 0 |
OutputsKnown_A | 24985807 | 24448827 | 0 | 0 |
gen_flops.OutputDelay_A | 24985807 | 24427216 | 0 | 2862 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 954 | 954 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24985807 | 24448827 | 0 | 0 |
T1 | 1346 | 985 | 0 | 0 |
T2 | 1983 | 1839 | 0 | 0 |
T3 | 4893 | 4810 | 0 | 0 |
T4 | 2191 | 2136 | 0 | 0 |
T5 | 3482 | 3035 | 0 | 0 |
T6 | 22881 | 22729 | 0 | 0 |
T7 | 1696 | 1307 | 0 | 0 |
T8 | 1695 | 1627 | 0 | 0 |
T9 | 3253 | 3156 | 0 | 0 |
T10 | 3251 | 2876 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24985807 | 24427216 | 0 | 2862 |
T1 | 1346 | 970 | 0 | 3 |
T2 | 1983 | 1833 | 0 | 3 |
T3 | 4893 | 4807 | 0 | 3 |
T4 | 2191 | 2133 | 0 | 3 |
T5 | 3482 | 3017 | 0 | 3 |
T6 | 22881 | 22723 | 0 | 3 |
T7 | 1696 | 1292 | 0 | 3 |
T8 | 1695 | 1624 | 0 | 3 |
T9 | 3253 | 3153 | 0 | 3 |
T10 | 3251 | 2861 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |