Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	74957421	151736	0	0
StatusRise_A	74957421	169128	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74957421	151736	0	0
T3	14679	37	0	0
T4	6573	22	0	0
T5	10446	0	0	0
T6	68643	222	0	0
T7	5088	0	0	0
T8	5085	17	0	0
T9	9759	26	0	0
T10	9753	12	0	0
T14	160173	255	0	0
T20	1887654	2354	0	0
T22	0	15	0	0
T25	0	30	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74957421	169128	0	0
T1	4038	15	0	0
T2	5949	6	0	0
T3	14679	40	0	0
T4	6573	24	0	0
T5	10446	18	0	0
T6	68643	228	0	0
T7	5088	15	0	0
T8	5085	19	0	0
T9	9759	29	0	0
T10	9753	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24985807	56339	0	0
StatusRise_A	24985807	62627	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	56339	0	0
T3	4893	14	0	0
T4	2191	7	0	0
T5	3482	0	0	0
T6	22881	85	0	0
T7	1696	0	0	0
T8	1695	6	0	0
T9	3253	10	0	0
T10	3251	4	0	0
T14	53391	92	0	0
T20	629218	877	0	0
T22	0	5	0	0
T25	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	62627	0	0
T1	1346	5	0	0
T2	1983	2	0	0
T3	4893	15	0	0
T4	2191	8	0	0
T5	3482	6	0	0
T6	22881	87	0	0
T7	1696	5	0	0
T8	1695	7	0	0
T9	3253	11	0	0
T10	3251	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24985807	56339	0	0
StatusRise_A	24985807	62628	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	56339	0	0
T3	4893	14	0	0
T4	2191	7	0	0
T5	3482	0	0	0
T6	22881	85	0	0
T7	1696	0	0	0
T8	1695	6	0	0
T9	3253	10	0	0
T10	3251	4	0	0
T14	53391	92	0	0
T20	629218	877	0	0
T22	0	5	0	0
T25	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	62628	0	0
T1	1346	5	0	0
T2	1983	2	0	0
T3	4893	15	0	0
T4	2191	8	0	0
T5	3482	6	0	0
T6	22881	87	0	0
T7	1696	5	0	0
T8	1695	7	0	0
T9	3253	11	0	0
T10	3251	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24985807	39058	0	0
StatusRise_A	24985807	43873	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	39058	0	0
T3	4893	9	0	0
T4	2191	8	0	0
T5	3482	0	0	0
T6	22881	52	0	0
T7	1696	0	0	0
T8	1695	5	0	0
T9	3253	6	0	0
T10	3251	4	0	0
T14	53391	71	0	0
T20	629218	600	0	0
T22	0	5	0	0
T25	0	10	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	43873	0	0
T1	1346	5	0	0
T2	1983	2	0	0
T3	4893	10	0	0
T4	2191	8	0	0
T5	3482	6	0	0
T6	22881	54	0	0
T7	1696	5	0	0
T8	1695	5	0	0
T9	3253	7	0	0
T10	3251	5	0	0