Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24986415	5324	0	0
EscTimeoutStoppedByClReset_A	24985807	3473829	0	0
EscTimeoutTriggersReset_A	5411145	307	0	0
RomAllowActiveState_A	24985807	62236	0	0
RomAllowCheckGoodState_A	24985807	62286	0	0
RomBlockActiveState_A	24985807	29184	0	0
RomBlockCheckGoodState_A	24985807	441913	0	0
RomIntgChkDisFalse_A	24985807	24304860	0	0
RomIntgChkDisTrue_A	24985807	143967	0	0
RstreqChkEsctimeout_A	24985807	4393	0	0
RstreqChkFsmterm_A	24985807	140	0	0
RstreqChkGlbesc_A	24985807	4393	0	0
RstreqChkMainpd_A	24985807	1016338	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24986415	5324	0	0
T11	15177	56	0	0
T12	14883	37	0	0
T13	0	26	0	0
T21	370742	0	0	0
T24	17045	0	0	0
T42	7268	0	0	0
T46	2573	0	0	0
T81	2099	0	0	0
T82	5999	0	0	0
T83	100559	0	0	0
T131	0	6	0	0
T132	0	72	0	0
T133	0	145	0	0
T134	0	7	0	0
T135	0	129	0	0
T136	0	35	0	0
T137	0	1	0	0
T138	1357	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	3473829	0	0
T1	1346	39	0	0
T2	1983	41	0	0
T3	4893	577	0	0
T4	2191	45	0	0
T5	3482	60	0	0
T6	22881	3004	0	0
T7	1696	18	0	0
T8	1695	16	0	0
T9	3253	397	0	0
T10	3251	113	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5411145	307	0	0
T11	678	3	0	0
T12	837	3	0	0
T13	0	2	0	0
T21	37195	0	0	0
T24	6939	0	0	0
T42	569	0	0	0
T46	301	0	0	0
T81	320	0	0	0
T82	1274	0	0	0
T83	18942	0	0	0
T131	0	4	0	0
T132	0	2	0	0
T133	0	3	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	0	3	0	0
T138	377	0	0	0
T139	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	62236	0	0
T1	1346	5	0	0
T2	1983	2	0	0
T3	4893	15	0	0
T4	2191	8	0	0
T5	3482	6	0	0
T6	22881	87	0	0
T7	1696	5	0	0
T8	1695	7	0	0
T9	3253	11	0	0
T10	3251	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	62286	0	0
T1	1346	5	0	0
T2	1983	2	0	0
T3	4893	15	0	0
T4	2191	8	0	0
T5	3482	6	0	0
T6	22881	87	0	0
T7	1696	5	0	0
T8	1695	7	0	0
T9	3253	11	0	0
T10	3251	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	29184	0	0
T6	22881	2	0	0
T7	1696	0	0	0
T8	1695	0	0	0
T9	3253	0	0	0
T10	3251	0	0	0
T14	53391	0	0	0
T20	629218	0	0	0
T22	1965	248	0	0
T23	0	17	0	0
T24	0	16	0	0
T25	1635	0	0	0
T29	0	32	0	0
T41	9332	0	0	0
T140	0	605	0	0
T141	0	1496	0	0
T142	0	7	0	0
T143	0	912	0	0
T144	0	26	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	441913	0	0
T6	22881	1293	0	0
T7	1696	0	0	0
T8	1695	0	0	0
T9	3253	0	0	0
T10	3251	0	0	0
T14	53391	45	0	0
T20	629218	3737	0	0
T21	0	2687	0	0
T22	1965	37	0	0
T23	0	1032	0	0
T24	0	1274	0	0
T25	1635	0	0	0
T28	0	598	0	0
T37	0	776	0	0
T41	9332	0	0	0
T83	0	1467	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	24304860	0	0
T1	1346	985	0	0
T2	1983	1839	0	0
T3	4893	4810	0	0
T4	2191	2136	0	0
T5	3482	3035	0	0
T6	22881	22729	0	0
T7	1696	1307	0	0
T8	1695	1627	0	0
T9	3253	3156	0	0
T10	3251	2876	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	143967	0	0
T22	1965	653	0	0
T23	18513	384	0	0
T24	0	417	0	0
T25	1635	0	0	0
T29	0	615	0	0
T37	65135	0	0	0
T38	2879	0	0	0
T41	9332	0	0	0
T43	5399	0	0	0
T44	2701	0	0	0
T45	1705	0	0	0
T80	10388	0	0	0
T140	0	156	0	0
T141	0	1773	0	0
T142	0	134	0	0
T143	0	682	0	0
T144	0	259	0	0
T145	0	757	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	4393	0	0
T2	1983	1	0	0
T3	4893	0	0	0
T4	2191	0	0	0
T5	3482	5	0	0
T6	22881	0	0	0
T7	1696	4	0	0
T8	1695	0	0	0
T9	3253	0	0	0
T10	3251	0	0	0
T14	53391	1	0	0
T20	0	53	0	0
T22	0	1	0	0
T25	0	4	0	0
T37	0	8	0	0
T38	0	1	0	0
T39	0	9	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	140	0	0
T17	7752	20	0	0
T18	0	20	0	0
T19	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	53293	0	0	0
T29	16723	0	0	0
T30	10328	0	0	0
T31	3386	0	0	0
T32	1662	0	0	0
T33	1629	0	0	0
T34	5772	0	0	0
T35	19127	0	0	0
T36	1958	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	4393	0	0
T2	1983	1	0	0
T3	4893	0	0	0
T4	2191	0	0	0
T5	3482	5	0	0
T6	22881	0	0	0
T7	1696	4	0	0
T8	1695	0	0	0
T9	3253	0	0	0
T10	3251	0	0	0
T14	53391	1	0	0
T20	0	53	0	0
T22	0	1	0	0
T25	0	4	0	0
T37	0	8	0	0
T38	0	1	0	0
T39	0	9	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24985807	1016338	0	0
T1	1346	17	0	0
T2	1983	0	0	0
T3	4893	0	0	0
T4	2191	0	0	0
T5	3482	0	0	0
T6	22881	2172	0	0
T7	1696	0	0	0
T8	1695	0	0	0
T9	3253	0	0	0
T10	3251	0	0	0
T14	0	428	0	0
T20	0	17611	0	0
T22	0	104	0	0
T23	0	1260	0	0
T25	0	135	0	0
T37	0	4714	0	0
T38	0	238	0	0
T39	0	221	0	0