Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208707

1

T1

16

T2

1

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	394096	1			T1	22		T2	1		T3	44
values[0x0]	175662	1			T1	18		T3	8		T4	21
values[0x1]	175519	1			T1	15		T3	8		T4	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	424950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

320327

1

T1

20

T2

1

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4416	1			T6	10		T14	66		T37	2
valid_sources[0x01]	3201	1			T4	2		T6	7		T14	56
valid_sources[0x02]	3202	1			T3	1		T6	8		T7	1
valid_sources[0x03]	2241	1			T6	10		T14	14		T56	1
valid_sources[0x04]	2079	1			T4	5		T6	10		T7	1
valid_sources[0x05]	2204	1			T6	6		T14	50		T37	1
valid_sources[0x06]	2249	1			T6	6		T37	3		T39	2
valid_sources[0x07]	2293	1			T6	5		T37	5		T22	12
valid_sources[0x08]	2274	1			T6	7		T14	72		T43	1
valid_sources[0x09]	3700	1			T4	2		T6	6		T14	64
valid_sources[0x0a]	2573	1			T6	11		T7	2		T10	4
valid_sources[0x0b]	3808	1			T6	9		T11	1		T14	5
valid_sources[0x0c]	2119	1			T3	1		T6	5		T14	19
valid_sources[0x0d]	2568	1			T6	6		T7	2		T14	117
valid_sources[0x0e]	1959	1			T6	5		T7	1		T14	18
valid_sources[0x0f]	2754	1			T6	10		T7	2		T37	5
valid_sources[0x10]	2124	1			T3	1		T6	9		T8	1
valid_sources[0x11]	2167	1			T6	6		T14	123		T37	2
valid_sources[0x12]	2135	1			T4	1		T6	2		T7	1
valid_sources[0x13]	2811	1			T6	5		T14	35		T37	3
valid_sources[0x14]	2242	1			T6	6		T14	14		T56	3
valid_sources[0x15]	2052	1			T6	10		T7	10		T70	6
valid_sources[0x16]	2593	1			T6	4		T14	51		T56	1
valid_sources[0x17]	2808	1			T6	13		T7	1		T14	77
valid_sources[0x18]	3183	1			T4	2		T6	10		T14	88
valid_sources[0x19]	2962	1			T4	2		T6	9		T14	80
valid_sources[0x1a]	2231	1			T3	1		T6	2		T10	1
valid_sources[0x1b]	4740	1			T6	10		T37	3		T25	4
valid_sources[0x1c]	3113	1			T6	2		T7	7		T90	7
valid_sources[0x1d]	2377	1			T4	1		T6	10		T90	5
valid_sources[0x1e]	2167	1			T6	12		T14	25		T37	3
valid_sources[0x1f]	4100	1			T4	1		T6	6		T7	2
valid_sources[0x20]	2745	1			T6	3		T7	2		T37	3
valid_sources[0x21]	6071	1			T6	3		T8	1		T14	24
valid_sources[0x22]	2227	1			T4	1		T6	8		T14	54
valid_sources[0x23]	2415	1			T3	1		T6	9		T7	3
valid_sources[0x24]	3620	1			T6	9		T14	36		T37	3
valid_sources[0x25]	2447	1			T3	1		T6	5		T14	5
valid_sources[0x26]	2612	1			T6	5		T14	17		T37	4
valid_sources[0x27]	2468	1			T6	3		T8	1		T14	54
valid_sources[0x28]	2276	1			T6	12		T14	16		T37	2
valid_sources[0x29]	2707	1			T6	6		T14	12		T37	4
valid_sources[0x2a]	2099	1			T6	13		T8	1		T14	25
valid_sources[0x2b]	2317	1			T4	5		T6	5		T7	5
valid_sources[0x2c]	2783	1			T6	11		T7	6		T10	4
valid_sources[0x2d]	2029	1			T1	3		T6	7		T14	24
valid_sources[0x2e]	2203	1			T6	6		T7	4		T10	2
valid_sources[0x2f]	3185	1			T6	5		T37	3		T25	3
valid_sources[0x30]	2559	1			T3	1		T6	5		T14	12
valid_sources[0x31]	2098	1			T4	1		T6	4		T8	2
valid_sources[0x32]	2181	1			T6	11		T7	1		T8	2
valid_sources[0x33]	2188	1			T4	4		T6	4		T37	5
valid_sources[0x34]	2861	1			T6	9		T14	282		T37	3
valid_sources[0x35]	2367	1			T6	4		T14	35		T37	3
valid_sources[0x36]	3081	1			T6	4		T14	91		T56	2
valid_sources[0x37]	2402	1			T6	8		T14	51		T37	3
valid_sources[0x38]	4674	1			T6	2		T7	2		T37	1
valid_sources[0x39]	2370	1			T6	6		T14	6		T37	2
valid_sources[0x3a]	2206	1			T1	3		T3	1		T6	10
valid_sources[0x3b]	2101	1			T6	4		T14	27		T12	1
valid_sources[0x3c]	2806	1			T6	9		T14	26		T37	3
valid_sources[0x3d]	2231	1			T6	6		T14	83		T37	7
valid_sources[0x3e]	3377	1			T3	1		T6	5		T7	2
valid_sources[0x3f]	3374	1			T6	6		T7	5		T14	35
valid_sources[0x40]	2092	1			T6	7		T14	30		T40	1
valid_sources[0x41]	2539	1			T4	3		T6	5		T14	21
valid_sources[0x42]	3221	1			T3	2		T6	4		T14	44
valid_sources[0x43]	2086	1			T3	1		T6	7		T10	7
valid_sources[0x44]	2270	1			T6	7		T7	3		T14	5
valid_sources[0x45]	2425	1			T6	8		T14	27		T37	1
valid_sources[0x46]	2789	1			T3	1		T4	1		T6	4
valid_sources[0x47]	3806	1			T4	1		T6	6		T14	160
valid_sources[0x48]	2183	1			T5	1		T6	7		T14	16
valid_sources[0x49]	2051	1			T4	4		T6	3		T14	31
valid_sources[0x4a]	2627	1			T4	6		T6	7		T10	5
valid_sources[0x4b]	2261	1			T6	5		T14	14		T37	3
valid_sources[0x4c]	2265	1			T3	1		T6	5		T7	1
valid_sources[0x4d]	3519	1			T6	11		T8	1		T14	6
valid_sources[0x4e]	2741	1			T6	10		T14	6		T70	9
valid_sources[0x4f]	3270	1			T3	3		T6	13		T8	2
valid_sources[0x50]	2891	1			T4	1		T6	6		T14	5
valid_sources[0x51]	3815	1			T6	9		T7	3		T14	5
valid_sources[0x52]	2059	1			T1	2		T4	1		T6	4
valid_sources[0x53]	2994	1			T3	1		T6	5		T7	2
valid_sources[0x54]	4608	1			T1	1		T4	3		T6	3
valid_sources[0x55]	2068	1			T6	11		T14	51		T37	4
valid_sources[0x56]	2367	1			T6	14		T14	77		T37	7
valid_sources[0x57]	2325	1			T6	5		T14	14		T37	3
valid_sources[0x58]	3196	1			T4	3		T6	5		T14	5
valid_sources[0x59]	3797	1			T1	2		T4	1		T6	7
valid_sources[0x5a]	3009	1			T6	6		T9	862		T14	8
valid_sources[0x5b]	2494	1			T6	5		T14	22		T37	4
valid_sources[0x5c]	2023	1			T6	15		T70	5		T37	5
valid_sources[0x5d]	2041	1			T6	6		T10	2		T22	12
valid_sources[0x5e]	2647	1			T6	3		T7	11		T14	64
valid_sources[0x5f]	3084	1			T6	3		T7	1		T14	32
valid_sources[0x60]	1971	1			T4	1		T6	5		T37	1
valid_sources[0x61]	3104	1			T1	2		T6	9		T7	3
valid_sources[0x62]	2540	1			T3	1		T4	1		T6	8
valid_sources[0x63]	4055	1			T3	1		T6	2		T7	1
valid_sources[0x64]	2104	1			T1	10		T6	9		T14	56
valid_sources[0x65]	2794	1			T1	1		T6	8		T7	2
valid_sources[0x66]	3174	1			T14	59		T37	5		T22	39
valid_sources[0x67]	2222	1			T3	2		T6	5		T14	11
valid_sources[0x68]	3807	1			T6	7		T14	54		T37	3
valid_sources[0x69]	3430	1			T1	1		T6	8		T14	121
valid_sources[0x6a]	5412	1			T3	1		T6	8		T14	84
valid_sources[0x6b]	2528	1			T6	8		T7	8		T10	1
valid_sources[0x6c]	2491	1			T3	1		T6	5		T14	96
valid_sources[0x6d]	2287	1			T6	13		T10	4		T14	33
valid_sources[0x6e]	2214	1			T6	6		T56	3		T37	3
valid_sources[0x6f]	3359	1			T1	3		T6	8		T10	1
valid_sources[0x70]	3832	1			T6	6		T14	149		T37	3
valid_sources[0x71]	2054	1			T6	8		T7	2		T37	5
valid_sources[0x72]	2183	1			T4	3		T6	4		T14	27
valid_sources[0x73]	2200	1			T6	10		T7	4		T56	5
valid_sources[0x74]	3425	1			T6	4		T7	4		T14	99
valid_sources[0x75]	2194	1			T6	4		T14	13		T37	2
valid_sources[0x76]	3530	1			T6	6		T8	3		T14	96
valid_sources[0x77]	2055	1			T6	7		T7	3		T10	27
valid_sources[0x78]	3172	1			T6	11		T14	78		T22	12
valid_sources[0x79]	2196	1			T6	7		T14	8		T56	7
valid_sources[0x7a]	3122	1			T6	7		T56	5		T37	2
valid_sources[0x7b]	2586	1			T6	7		T37	1		T25	1
valid_sources[0x7c]	2214	1			T4	1		T6	10		T10	3
valid_sources[0x7d]	5410	1			T6	9		T14	66		T37	4
valid_sources[0x7e]	3807	1			T6	6		T7	2		T10	17
valid_sources[0x7f]	2361	1			T6	8		T14	82		T15	1
valid_sources[0x80]	2208	1			T6	5		T14	9		T37	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

108153

1

T1

8

T2

1

T3

19

values[0x0]

all_enables

biggest_size

65200

1

T1

5

T3

3

T4

10

values[0x1]

all_enables

biggest_size

35354

1

T1

3

T3

1

T4

8