SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34762 | 1 | T9 | 310 | T21 | 379 | T37 | 399 | ||||
others[1] | 35181 | 1 | T9 | 300 | T21 | 405 | T37 | 405 | ||||
others[2] | 35068 | 1 | T9 | 289 | T21 | 404 | T37 | 422 | ||||
others[3] | 58387 | 1 | T9 | 517 | T21 | 669 | T37 | 650 | ||||
false | 19744 | 1 | T4 | 10 | T6 | 44 | T9 | 50 | ||||
true | 29915 | 1 | T1 | 12 | T2 | 5 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34890 | 1 | T9 | 307 | T21 | 403 | T37 | 367 | ||||
others[1] | 34823 | 1 | T9 | 294 | T21 | 360 | T37 | 411 | ||||
others[2] | 35282 | 1 | T9 | 301 | T21 | 389 | T37 | 403 | ||||
others[3] | 58446 | 1 | T9 | 505 | T21 | 697 | T37 | 696 | ||||
false | 12473 | 1 | T4 | 5 | T6 | 22 | T9 | 50 | ||||
true | 22714 | 1 | T1 | 12 | T2 | 5 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 705 | 1 | T7 | 5 | T14 | 4 | T166 | 8 | ||||
others[1] | 753 | 1 | T7 | 7 | T14 | 7 | T166 | 8 | ||||
others[2] | 694 | 1 | T7 | 6 | T14 | 8 | T24 | 1 | ||||
others[3] | 1135 | 1 | T1 | 1 | T7 | 6 | T14 | 13 | ||||
false | 13911 | 1 | T1 | 17 | T2 | 5 | T3 | 5 | ||||
true | 4058 | 1 | T1 | 4 | T7 | 3 | T14 | 66 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |