Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24902954	6469	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24902954	272565	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24902954	10358300	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24902954	272543	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24902954	6469	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24902954	272565	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24902954	10358300	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24902954	272543	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	6469	0	0
T3	3404	1	0	0
T4	2335	5	0	0
T5	2667	0	0	0
T6	38159	13	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	23	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	76	0	0
T21	0	19	0	0
T37	0	18	0	0
T38	0	9	0	0
T49	0	2	0	0
T90	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	272565	0	0
T3	3404	232	0	0
T4	2335	148	0	0
T5	2667	0	0	0
T6	38159	410	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	584	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	5407	0	0
T21	0	1130	0	0
T37	0	423	0	0
T38	0	441	0	0
T49	0	164	0	0
T90	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	10358300	0	0
T3	3404	163	0	0
T4	2335	1580	0	0
T5	2667	0	0	0
T6	38159	19976	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	7694	0	0
T10	2049	1155	0	0
T11	567	0	0	0
T14	279775	119061	0	0
T21	0	23805	0	0
T56	0	536	0	0
T70	0	1534	0	0
T90	0	830	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	272543	0	0
T3	3404	232	0	0
T4	2335	148	0	0
T5	2667	0	0	0
T6	38159	410	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	584	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	5410	0	0
T21	0	1130	0	0
T37	0	423	0	0
T38	0	441	0	0
T49	0	164	0	0
T90	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	6469	0	0
T3	3404	1	0	0
T4	2335	5	0	0
T5	2667	0	0	0
T6	38159	13	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	23	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	76	0	0
T21	0	19	0	0
T37	0	18	0	0
T38	0	9	0	0
T49	0	2	0	0
T90	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	272565	0	0
T3	3404	232	0	0
T4	2335	148	0	0
T5	2667	0	0	0
T6	38159	410	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	584	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	5407	0	0
T21	0	1130	0	0
T37	0	423	0	0
T38	0	441	0	0
T49	0	164	0	0
T90	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	10358300	0	0
T3	3404	163	0	0
T4	2335	1580	0	0
T5	2667	0	0	0
T6	38159	19976	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	7694	0	0
T10	2049	1155	0	0
T11	567	0	0	0
T14	279775	119061	0	0
T21	0	23805	0	0
T56	0	536	0	0
T70	0	1534	0	0
T90	0	830	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	272543	0	0
T3	3404	232	0	0
T4	2335	148	0	0
T5	2667	0	0	0
T6	38159	410	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	584	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	5410	0	0
T21	0	1130	0	0
T37	0	423	0	0
T38	0	441	0	0
T49	0	164	0	0
T90	0	12	0	0