Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25521201	14601	0	0
intr_enable_rd_A	25521201	40779	0	0
reset_en_rd_A	25521201	1005	0	0
reset_en_regwen_rd_A	25521201	884	0	0
wake_info_capture_dis_rd_A	25521201	891	0	0
wakeup_en_rd_A	25521201	1769	0	0
wakeup_en_regwen_rd_A	25521201	943	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	14601	0	0
T12	2323	0	0	0
T13	817	0	0	0
T14	279775	65	0	0
T15	1610	0	0	0
T21	51882	0	0	0
T22	0	10	0	0
T23	0	6	0	0
T24	5432	0	0	0
T43	1916	0	0	0
T51	0	91	0	0
T56	5766	0	0	0
T70	10425	0	0	0
T85	0	12	0	0
T90	1005	0	0	0
T92	0	31	0	0
T93	0	29	0	0
T140	0	11	0	0
T141	0	7	0	0
T142	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	40779	0	0
T12	2323	0	0	0
T13	817	0	0	0
T15	1610	0	0	0
T21	51882	122	0	0
T24	5432	0	0	0
T25	0	135	0	0
T38	0	34	0	0
T40	14905	0	0	0
T43	1916	0	0	0
T44	0	22	0	0
T56	5766	0	0	0
T63	0	17	0	0
T64	0	84	0	0
T70	10425	0	0	0
T90	1005	0	0	0
T91	0	9	0	0
T111	0	6	0	0
T143	0	21	0	0
T144	0	24	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	1005	0	0
T23	142873	10	0	0
T67	0	23	0	0
T81	0	9	0	0
T108	0	22	0	0
T116	30877	0	0	0
T145	0	3	0	0
T146	0	3	0	0
T147	0	4	0	0
T148	0	11	0	0
T149	0	10	0	0
T150	0	6	0	0
T151	4705	0	0	0
T152	2075	0	0	0
T153	2430	0	0	0
T154	15036	0	0	0
T155	424	0	0	0
T156	1349	0	0	0
T157	6000	0	0	0
T158	10575	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	884	0	0
T23	142873	14	0	0
T60	0	1	0	0
T108	0	24	0	0
T116	30877	0	0	0
T145	0	9	0	0
T146	0	4	0	0
T147	0	9	0	0
T148	0	3	0	0
T149	0	5	0	0
T151	4705	0	0	0
T152	2075	0	0	0
T153	2430	0	0	0
T154	15036	0	0	0
T155	424	0	0	0
T156	1349	0	0	0
T157	6000	0	0	0
T158	10575	0	0	0
T159	0	4	0	0
T160	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	891	0	0
T23	142873	12	0	0
T60	0	5	0	0
T108	0	15	0	0
T116	30877	0	0	0
T145	0	8	0	0
T146	0	9	0	0
T147	0	12	0	0
T148	0	6	0	0
T149	0	8	0	0
T150	0	8	0	0
T151	4705	0	0	0
T152	2075	0	0	0
T153	2430	0	0	0
T154	15036	0	0	0
T155	424	0	0	0
T156	1349	0	0	0
T157	6000	0	0	0
T158	10575	0	0	0
T159	0	11	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	1769	0	0
T23	142873	8	0	0
T57	0	98	0	0
T67	0	31	0	0
T108	0	21	0	0
T116	30877	0	0	0
T145	0	8	0	0
T146	0	5	0	0
T147	0	16	0	0
T148	0	26	0	0
T149	0	20	0	0
T151	4705	0	0	0
T152	2075	0	0	0
T153	2430	0	0	0
T154	15036	0	0	0
T155	424	0	0	0
T156	1349	0	0	0
T157	6000	0	0	0
T158	10575	0	0	0
T161	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25521201	943	0	0
T23	142873	2	0	0
T108	0	16	0	0
T116	30877	0	0	0
T145	0	4	0	0
T146	0	5	0	0
T147	0	12	0	0
T148	0	8	0	0
T149	0	5	0	0
T150	0	1	0	0
T151	4705	0	0	0
T152	2075	0	0	0
T153	2430	0	0	0
T154	15036	0	0	0
T155	424	0	0	0
T156	1349	0	0	0
T157	6000	0	0	0
T158	10575	0	0	0
T159	0	4	0	0
T161	0	8	0	0