Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	74708862	149815	0	0
StatusRise_A	74708862	166988	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74708862	149815	0	0
T1	10020	54	0	0
T2	4506	0	0	0
T3	10212	12	0	0
T4	7005	25	0	0
T5	8001	0	0	0
T6	114477	324	0	0
T7	6747	9	0	0
T8	3849	12	0	0
T9	50502	216	0	0
T10	6147	18	0	0
T11	0	3	0	0
T14	0	1622	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74708862	166988	0	0
T1	10020	57	0	0
T2	4506	15	0	0
T3	10212	15	0	0
T4	7005	30	0	0
T5	8001	9	0	0
T6	114477	362	0	0
T7	6747	12	0	0
T8	3849	15	0	0
T9	50502	221	0	0
T10	6147	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24902954	55583	0	0
StatusRise_A	24902954	61804	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	55583	0	0
T1	3340	18	0	0
T2	1502	0	0	0
T3	3404	4	0	0
T4	2335	10	0	0
T5	2667	0	0	0
T6	38159	122	0	0
T7	2249	3	0	0
T8	1283	4	0	0
T9	16834	84	0	0
T10	2049	6	0	0
T11	0	1	0	0
T14	0	591	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	61804	0	0
T1	3340	19	0	0
T2	1502	5	0	0
T3	3404	5	0	0
T4	2335	12	0	0
T5	2667	3	0	0
T6	38159	136	0	0
T7	2249	4	0	0
T8	1283	5	0	0
T9	16834	86	0	0
T10	2049	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24902954	55583	0	0
StatusRise_A	24902954	61807	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	55583	0	0
T1	3340	18	0	0
T2	1502	0	0	0
T3	3404	4	0	0
T4	2335	10	0	0
T5	2667	0	0	0
T6	38159	122	0	0
T7	2249	3	0	0
T8	1283	4	0	0
T9	16834	84	0	0
T10	2049	6	0	0
T11	0	1	0	0
T14	0	591	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	61807	0	0
T1	3340	19	0	0
T2	1502	5	0	0
T3	3404	5	0	0
T4	2335	12	0	0
T5	2667	3	0	0
T6	38159	136	0	0
T7	2249	4	0	0
T8	1283	5	0	0
T9	16834	86	0	0
T10	2049	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24902954	38649	0	0
StatusRise_A	24902954	43377	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	38649	0	0
T1	3340	18	0	0
T2	1502	0	0	0
T3	3404	4	0	0
T4	2335	5	0	0
T5	2667	0	0	0
T6	38159	80	0	0
T7	2249	3	0	0
T8	1283	4	0	0
T9	16834	48	0	0
T10	2049	6	0	0
T11	0	1	0	0
T14	0	440	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	43377	0	0
T1	3340	19	0	0
T2	1502	5	0	0
T3	3404	5	0	0
T4	2335	6	0	0
T5	2667	3	0	0
T6	38159	90	0	0
T7	2249	4	0	0
T8	1283	5	0	0
T9	16834	49	0	0
T10	2049	6	0	0