Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24903544	5697	0	0
EscTimeoutStoppedByClReset_A	24902954	3555571	0	0
EscTimeoutTriggersReset_A	4956585	318	0	0
RomAllowActiveState_A	24902954	61405	0	0
RomAllowCheckGoodState_A	24902954	61455	0	0
RomBlockActiveState_A	24902954	29066	0	0
RomBlockCheckGoodState_A	24902954	447315	0	0
RomIntgChkDisFalse_A	24902954	24197498	0	0
RomIntgChkDisTrue_A	24902954	172227	0	0
RstreqChkEsctimeout_A	24902954	4403	0	0
RstreqChkFsmterm_A	24902954	160	0	0
RstreqChkGlbesc_A	24902954	4403	0	0
RstreqChkMainpd_A	24902954	1039338	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24903544	5697	0	0
T13	818	2	0	0
T22	302837	0	0	0
T36	0	48	0	0
T37	18776	0	0	0
T38	11361	0	0	0
T39	11549	0	0	0
T40	14906	55	0	0
T42	0	175	0	0
T49	1736	0	0	0
T62	17029	0	0	0
T63	4449	0	0	0
T110	0	12	0	0
T153	0	20	0	0
T162	0	13	0	0
T163	0	241	0	0
T164	0	30	0	0
T165	0	131	0	0
T166	4509	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	3555571	0	0
T1	3340	279	0	0
T2	1502	46	0	0
T3	3404	81	0	0
T4	2335	174	0	0
T5	2667	22	0	0
T6	38159	5189	0	0
T7	2249	40	0	0
T8	1283	65	0	0
T9	16834	3500	0	0
T10	2049	44	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4956585	318	0	0
T11	391	7	0	0
T12	205	2	0	0
T13	0	3	0	0
T14	28174	0	0	0
T15	417	0	0	0
T21	6469	0	0	0
T24	402	0	0	0
T36	0	3	0	0
T40	0	3	0	0
T42	0	2	0	0
T43	340	0	0	0
T56	1145	0	0	0
T70	1348	0	0	0
T90	922	0	0	0
T110	0	3	0	0
T162	0	4	0	0
T163	0	3	0	0
T164	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	61405	0	0
T1	3340	12	0	0
T2	1502	5	0	0
T3	3404	5	0	0
T4	2335	12	0	0
T5	2667	3	0	0
T6	38159	136	0	0
T7	2249	4	0	0
T8	1283	5	0	0
T9	16834	86	0	0
T10	2049	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	61455	0	0
T1	3340	13	0	0
T2	1502	5	0	0
T3	3404	5	0	0
T4	2335	12	0	0
T5	2667	3	0	0
T6	38159	136	0	0
T7	2249	4	0	0
T8	1283	5	0	0
T9	16834	86	0	0
T10	2049	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	29066	0	0
T12	2323	0	0	0
T13	817	0	0	0
T15	1610	0	0	0
T24	5432	1244	0	0
T37	18775	3	0	0
T40	14905	0	0	0
T43	1916	0	0	0
T50	0	4	0	0
T56	5766	0	0	0
T70	10425	0	0	0
T90	1005	0	0	0
T151	0	587	0	0
T167	0	20	0	0
T168	0	1086	0	0
T169	0	128	0	0
T170	0	12	0	0
T171	0	3	0	0
T172	0	9	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	447315	0	0
T4	2335	114	0	0
T5	2667	0	0	0
T6	38159	505	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	1303	0	0
T10	2049	0	0	0
T11	567	0	0	0
T14	279775	3280	0	0
T21	51882	3512	0	0
T22	0	5273	0	0
T24	0	1035	0	0
T37	0	1288	0	0
T38	0	366	0	0
T39	0	207	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	24197498	0	0
T1	3340	2430	0	0
T2	1502	1158	0	0
T3	3404	3007	0	0
T4	2335	2179	0	0
T5	2667	2414	0	0
T6	38159	37028	0	0
T7	2249	2168	0	0
T8	1283	922	0	0
T9	16834	16400	0	0
T10	2049	1997	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	172227	0	0
T9	16834	279	0	0
T10	2049	0	0	0
T11	567	0	0	0
T12	2323	0	0	0
T14	279775	0	0	0
T15	1610	0	0	0
T21	51882	0	0	0
T24	5432	1448	0	0
T25	0	2530	0	0
T35	0	1604	0	0
T50	0	175	0	0
T56	5766	0	0	0
T90	1005	0	0	0
T168	0	2365	0	0
T169	0	122	0	0
T170	0	512	0	0
T173	0	16597	0	0
T174	0	526	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	4403	0	0
T1	3340	4	0	0
T2	1502	4	0	0
T3	3404	0	0	0
T4	2335	0	0	0
T5	2667	0	0	0
T6	38159	0	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	0	0	0
T10	2049	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	71	0	0
T22	0	79	0	0
T24	0	2	0	0
T40	0	1	0	0
T43	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	160	0	0
T18	44194	40	0	0
T19	0	40	0	0
T20	0	40	0	0
T26	0	20	0	0
T27	0	20	0	0
T28	4470	0	0	0
T29	2050	0	0	0
T30	4491	0	0	0
T31	7201	0	0	0
T32	3114	0	0	0
T33	3851	0	0	0
T34	1885	0	0	0
T35	52932	0	0	0
T36	15083	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	4403	0	0
T1	3340	4	0	0
T2	1502	4	0	0
T3	3404	0	0	0
T4	2335	0	0	0
T5	2667	0	0	0
T6	38159	0	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	0	0	0
T10	2049	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	71	0	0
T22	0	79	0	0
T24	0	2	0	0
T40	0	1	0	0
T43	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24902954	1039338	0	0
T1	3340	85	0	0
T2	1502	0	0	0
T3	3404	0	0	0
T4	2335	312	0	0
T5	2667	5	0	0
T6	38159	887	0	0
T7	2249	0	0	0
T8	1283	0	0	0
T9	16834	1887	0	0
T10	2049	0	0	0
T14	0	22804	0	0
T15	0	22	0	0
T21	0	4260	0	0
T24	0	1071	0	0
T37	0	1517	0	0