Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	499065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

195078

1

T1

14

T2

18

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	364957	1			T1	31		T2	37		T3	1
values[0x0]	164427	1			T1	5		T2	11		T4	12
values[0x1]	164759	1			T1	1		T2	13		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	395215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

298928

1

T1

17

T2

31

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2296	1			T6	4		T9	1		T21	18
valid_sources[0x01]	2213	1			T4	3		T9	4		T10	1
valid_sources[0x02]	3111	1			T9	1		T10	1		T20	5
valid_sources[0x03]	2623	1			T9	8		T20	7		T22	15
valid_sources[0x04]	2424	1			T6	4		T9	4		T20	11
valid_sources[0x05]	2356	1			T4	1		T6	4		T9	3
valid_sources[0x06]	2295	1			T6	1		T13	11		T20	3
valid_sources[0x07]	2227	1			T6	4		T9	5		T20	4
valid_sources[0x08]	3202	1			T6	6		T9	7		T20	1
valid_sources[0x09]	2342	1			T9	1		T20	2		T14	2
valid_sources[0x0a]	3176	1			T1	2		T20	2		T21	11
valid_sources[0x0b]	2446	1			T9	6		T20	6		T14	1
valid_sources[0x0c]	3042	1			T7	11		T9	5		T20	2
valid_sources[0x0d]	3078	1			T9	6		T10	2		T20	8
valid_sources[0x0e]	2179	1			T6	15		T9	2		T20	2
valid_sources[0x0f]	2171	1			T8	1		T9	2		T10	1
valid_sources[0x10]	2407	1			T9	4		T20	1		T21	53
valid_sources[0x11]	2362	1			T8	1		T13	16		T20	1
valid_sources[0x12]	2680	1			T4	1		T9	6		T10	2
valid_sources[0x13]	2416	1			T6	6		T9	5		T20	2
valid_sources[0x14]	2620	1			T20	7		T14	4		T21	61
valid_sources[0x15]	3168	1			T9	1		T13	34		T20	1
valid_sources[0x16]	2369	1			T9	3		T13	11		T20	1
valid_sources[0x17]	2825	1			T9	2		T20	4		T21	20
valid_sources[0x18]	2469	1			T4	1		T9	4		T20	3
valid_sources[0x19]	2505	1			T6	9		T9	4		T20	4
valid_sources[0x1a]	3050	1			T4	1		T9	1		T20	3
valid_sources[0x1b]	2491	1			T9	3		T13	12		T20	12
valid_sources[0x1c]	2438	1			T9	2		T20	2		T21	7
valid_sources[0x1d]	2181	1			T8	1		T9	1		T20	4
valid_sources[0x1e]	2219	1			T9	9		T20	1		T14	1
valid_sources[0x1f]	2300	1			T5	1		T9	5		T20	2
valid_sources[0x20]	2236	1			T9	3		T20	3		T21	28
valid_sources[0x21]	2299	1			T6	3		T9	1		T10	1
valid_sources[0x22]	2012	1			T4	1		T20	2		T14	1
valid_sources[0x23]	3865	1			T9	1		T13	1405		T20	1
valid_sources[0x24]	2947	1			T9	7		T20	3		T21	10
valid_sources[0x25]	2366	1			T2	5		T9	1		T13	1
valid_sources[0x26]	2572	1			T9	2		T10	1		T20	2
valid_sources[0x27]	3461	1			T6	3		T9	1		T20	2
valid_sources[0x28]	3012	1			T6	2		T9	2		T13	12
valid_sources[0x29]	3107	1			T4	1		T9	3		T13	12
valid_sources[0x2a]	3497	1			T9	4		T13	12		T20	2
valid_sources[0x2b]	2899	1			T1	1		T4	1		T6	1
valid_sources[0x2c]	3249	1			T20	9		T21	33		T34	4
valid_sources[0x2d]	2623	1			T6	6		T9	9		T20	5
valid_sources[0x2e]	2924	1			T6	2		T9	4		T10	1
valid_sources[0x2f]	2220	1			T9	1		T13	11		T20	2
valid_sources[0x30]	2331	1			T1	1		T9	2		T13	12
valid_sources[0x31]	2263	1			T9	2		T20	2		T21	13
valid_sources[0x32]	2397	1			T9	2		T20	2		T21	33
valid_sources[0x33]	2422	1			T9	4		T10	1		T13	11
valid_sources[0x34]	2158	1			T1	2		T9	4		T10	1
valid_sources[0x35]	2170	1			T4	1		T9	4		T14	1
valid_sources[0x36]	2517	1			T9	3		T13	22		T20	6
valid_sources[0x37]	2333	1			T9	3		T20	5		T21	3
valid_sources[0x38]	2759	1			T9	1		T10	1		T13	12
valid_sources[0x39]	3750	1			T9	6		T10	2		T14	1
valid_sources[0x3a]	2601	1			T9	1		T13	22		T20	2
valid_sources[0x3b]	2261	1			T9	8		T20	2		T34	1
valid_sources[0x3c]	3221	1			T9	6		T20	3		T21	73
valid_sources[0x3d]	2350	1			T9	3		T10	2		T20	1
valid_sources[0x3e]	2718	1			T6	5		T9	1		T20	3
valid_sources[0x3f]	2203	1			T20	6		T14	1		T22	30
valid_sources[0x40]	2429	1			T4	1		T9	4		T13	1
valid_sources[0x41]	2116	1			T6	2		T9	3		T13	12
valid_sources[0x42]	5312	1			T4	1		T6	3		T9	2
valid_sources[0x43]	2695	1			T6	1		T9	3		T20	5
valid_sources[0x44]	2573	1			T4	1		T9	7		T13	11
valid_sources[0x45]	2327	1			T10	1		T13	11		T20	4
valid_sources[0x46]	2491	1			T4	1		T6	1		T9	2
valid_sources[0x47]	2555	1			T1	2		T6	2		T9	3
valid_sources[0x48]	2227	1			T6	2		T9	1		T10	1
valid_sources[0x49]	2423	1			T6	1		T9	2		T13	11
valid_sources[0x4a]	2326	1			T8	4		T9	2		T13	11
valid_sources[0x4b]	3248	1			T1	3		T9	4		T20	1
valid_sources[0x4c]	2412	1			T2	6		T6	1		T9	3
valid_sources[0x4d]	2995	1			T6	1		T9	4		T13	11
valid_sources[0x4e]	2650	1			T9	8		T20	5		T14	1
valid_sources[0x4f]	2400	1			T8	6		T14	3		T21	56
valid_sources[0x50]	2410	1			T9	2		T10	2		T20	1
valid_sources[0x51]	3562	1			T1	1		T6	5		T9	2
valid_sources[0x52]	2619	1			T20	4		T21	12		T22	33
valid_sources[0x53]	2270	1			T9	3		T13	7		T20	5
valid_sources[0x54]	2134	1			T6	4		T13	11		T20	5
valid_sources[0x55]	7058	1			T9	3		T20	5		T14	2
valid_sources[0x56]	2249	1			T1	2		T9	1		T20	3
valid_sources[0x57]	2192	1			T6	4		T9	9		T13	11
valid_sources[0x58]	2498	1			T9	4		T21	120		T22	19
valid_sources[0x59]	2238	1			T9	1		T20	8		T34	3
valid_sources[0x5a]	2588	1			T6	2		T9	2		T13	12
valid_sources[0x5b]	2349	1			T9	9		T20	4		T21	8
valid_sources[0x5c]	3563	1			T9	4		T20	3		T21	12
valid_sources[0x5d]	2603	1			T6	1		T9	2		T20	3
valid_sources[0x5e]	2432	1			T9	5		T10	1		T20	3
valid_sources[0x5f]	2052	1			T9	5		T20	7		T22	36
valid_sources[0x60]	2385	1			T9	3		T13	12		T20	4
valid_sources[0x61]	2166	1			T9	3		T10	1		T20	2
valid_sources[0x62]	2692	1			T9	6		T13	23		T20	4
valid_sources[0x63]	2314	1			T9	7		T10	1		T20	1
valid_sources[0x64]	2508	1			T4	1		T6	6		T9	1
valid_sources[0x65]	2322	1			T4	2		T9	3		T13	23
valid_sources[0x66]	2326	1			T4	1		T8	9		T20	2
valid_sources[0x67]	2097	1			T9	3		T10	1		T20	1
valid_sources[0x68]	3167	1			T9	2		T13	21		T20	5
valid_sources[0x69]	2507	1			T20	3		T14	1		T21	101
valid_sources[0x6a]	2367	1			T9	6		T20	5		T22	25
valid_sources[0x6b]	2607	1			T6	5		T9	4		T20	3
valid_sources[0x6c]	3465	1			T6	2		T9	2		T20	1
valid_sources[0x6d]	2417	1			T9	1		T13	11		T20	4
valid_sources[0x6e]	2507	1			T6	3		T9	6		T10	1
valid_sources[0x6f]	3873	1			T9	1		T10	1		T20	4
valid_sources[0x70]	10911	1			T9	5		T10	1		T13	822
valid_sources[0x71]	2421	1			T6	7		T9	3		T20	3
valid_sources[0x72]	2471	1			T9	3		T13	65		T20	6
valid_sources[0x73]	2495	1			T9	2		T20	4		T14	1
valid_sources[0x74]	2358	1			T9	4		T20	5		T22	20
valid_sources[0x75]	2272	1			T9	4		T20	7		T21	2
valid_sources[0x76]	2375	1			T10	1		T20	2		T14	1
valid_sources[0x77]	2764	1			T7	3		T9	2		T10	2
valid_sources[0x78]	2893	1			T9	3		T13	12		T20	4
valid_sources[0x79]	2424	1			T8	3		T9	3		T20	1
valid_sources[0x7a]	2333	1			T4	2		T9	1		T20	1
valid_sources[0x7b]	2303	1			T9	1		T20	5		T14	1
valid_sources[0x7c]	2435	1			T6	3		T9	2		T13	11
valid_sources[0x7d]	2259	1			T1	1		T9	1		T20	2
valid_sources[0x7e]	2394	1			T9	15		T20	6		T21	69
valid_sources[0x7f]	2438	1			T9	4		T13	12		T20	2
valid_sources[0x80]	2357	1			T4	1		T9	3		T13	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

99348

1

T1

14

T2

12

T3

1

values[0x0]

all_enables

biggest_size

61875

1

T2

3

T4

3

T6

9

values[0x1]

all_enables

biggest_size

33855

1

T2

3

T4

4

T6

5