SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35170 | 1 | T9 | 290 | T20 | 428 | T157 | 388 | ||||
others[1] | 35109 | 1 | T4 | 1 | T8 | 1 | T9 | 292 | ||||
others[2] | 34832 | 1 | T9 | 311 | T10 | 1 | T20 | 360 | ||||
others[3] | 58250 | 1 | T8 | 1 | T9 | 511 | T20 | 653 | ||||
false | 18246 | 1 | T4 | 3 | T8 | 2 | T9 | 50 | ||||
true | 28124 | 1 | T1 | 1 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35290 | 1 | T8 | 1 | T9 | 302 | T20 | 406 | ||||
others[1] | 34962 | 1 | T4 | 1 | T9 | 294 | T20 | 397 | ||||
others[2] | 34756 | 1 | T9 | 307 | T20 | 388 | T157 | 389 | ||||
others[3] | 58364 | 1 | T9 | 491 | T10 | 1 | T20 | 662 | ||||
false | 11730 | 1 | T4 | 2 | T8 | 3 | T9 | 50 | ||||
true | 21649 | 1 | T1 | 1 | T2 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 679 | 1 | T4 | 1 | T6 | 4 | T13 | 6 | ||||
others[1] | 662 | 1 | T4 | 1 | T6 | 4 | T13 | 16 | ||||
others[2] | 703 | 1 | T6 | 7 | T13 | 9 | T21 | 4 | ||||
others[3] | 1170 | 1 | T1 | 1 | T4 | 1 | T6 | 8 | ||||
false | 13481 | 1 | T1 | 2 | T2 | 1 | T3 | 3 | ||||
true | 4045 | 1 | T4 | 1 | T6 | 1 | T8 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |