Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T13
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T20

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24148617	5998	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24148617	261008	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24148617	10038289	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24148617	261026	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24148617	5998	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24148617	261008	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24148617	10038289	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24148617	261026	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	5998	0	0
T7	1516	2	0	0
T8	3740	0	0	0
T9	44407	27	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	51	0	0
T14	2887	0	0	0
T20	20713	27	0	0
T21	124605	32	0	0
T22	0	25	0	0
T34	6503	0	0	0
T36	0	80	0	0
T37	0	76	0	0
T38	0	2	0	0
T71	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	261008	0	0
T7	1516	158	0	0
T8	3740	0	0	0
T9	44407	1066	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	1365	0	0
T14	2887	0	0	0
T20	20713	580	0	0
T21	124605	973	0	0
T22	0	1372	0	0
T34	6503	0	0	0
T36	0	6261	0	0
T37	0	2301	0	0
T38	0	541	0	0
T71	0	15	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	10038289	0	0
T7	1516	217	0	0
T8	3740	0	0	0
T9	44407	24420	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	100972	0	0
T14	2887	1729	0	0
T20	20713	12764	0	0
T21	124605	50355	0	0
T22	0	130421	0	0
T34	6503	0	0	0
T36	0	284051	0	0
T72	0	1786	0	0
T73	0	2415	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	261026	0	0
T7	1516	158	0	0
T8	3740	0	0	0
T9	44407	1066	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	1365	0	0
T14	2887	0	0	0
T20	20713	580	0	0
T21	124605	971	0	0
T22	0	1374	0	0
T34	6503	0	0	0
T36	0	6258	0	0
T37	0	2301	0	0
T38	0	541	0	0
T71	0	15	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	5998	0	0
T7	1516	2	0	0
T8	3740	0	0	0
T9	44407	27	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	51	0	0
T14	2887	0	0	0
T20	20713	27	0	0
T21	124605	32	0	0
T22	0	25	0	0
T34	6503	0	0	0
T36	0	80	0	0
T37	0	76	0	0
T38	0	2	0	0
T71	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	261008	0	0
T7	1516	158	0	0
T8	3740	0	0	0
T9	44407	1066	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	1365	0	0
T14	2887	0	0	0
T20	20713	580	0	0
T21	124605	973	0	0
T22	0	1372	0	0
T34	6503	0	0	0
T36	0	6261	0	0
T37	0	2301	0	0
T38	0	541	0	0
T71	0	15	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	10038289	0	0
T7	1516	217	0	0
T8	3740	0	0	0
T9	44407	24420	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	100972	0	0
T14	2887	1729	0	0
T20	20713	12764	0	0
T21	124605	50355	0	0
T22	0	130421	0	0
T34	6503	0	0	0
T36	0	284051	0	0
T72	0	1786	0	0
T73	0	2415	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	261026	0	0
T7	1516	158	0	0
T8	3740	0	0	0
T9	44407	1066	0	0
T10	1743	0	0	0
T11	15167	0	0	0
T13	261585	1365	0	0
T14	2887	0	0	0
T20	20713	580	0	0
T21	124605	971	0	0
T22	0	1374	0	0
T34	6503	0	0	0
T36	0	6258	0	0
T37	0	2301	0	0
T38	0	541	0	0
T71	0	15	0	0