Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24694668	15968	0	0
intr_enable_rd_A	24694668	41469	0	0
reset_en_rd_A	24694668	1154	0	0
reset_en_regwen_rd_A	24694668	1088	0	0
wake_info_capture_dis_rd_A	24694668	1089	0	0
wakeup_en_rd_A	24694668	1558	0	0
wakeup_en_regwen_rd_A	24694668	1065	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	15968	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	9	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	4	0	0
T22	302792	8	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	24	0	0
T37	0	3	0	0
T46	0	37	0	0
T72	2711	0	0	0
T87	0	133	0	0
T127	0	5	0	0
T128	0	20	0	0
T129	0	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	41469	0	0
T6	4078	108	0	0
T7	1516	0	0	0
T8	3740	21	0	0
T9	44407	180	0	0
T10	1743	22	0	0
T11	15167	0	0	0
T13	261585	2445	0	0
T14	2887	42	0	0
T20	20713	124	0	0
T21	124605	0	0	0
T22	0	869	0	0
T36	0	3165	0	0
T37	0	896	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	1154	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	11	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	0	0	0
T22	302792	7	0	0
T33	0	15	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	15	0	0
T37	0	1	0	0
T46	0	19	0	0
T72	2711	0	0	0
T88	0	11	0	0
T130	0	8	0	0
T131	0	1	0	0
T132	0	7	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	1088	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	11	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	0	0	0
T22	302792	0	0	0
T33	0	13	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	15	0	0
T46	0	18	0	0
T72	2711	0	0	0
T88	0	7	0	0
T128	0	5	0	0
T129	0	7	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	1089	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	25	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	0	0	0
T22	302792	10	0	0
T33	0	8	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	9	0	0
T37	0	4	0	0
T46	0	21	0	0
T72	2711	0	0	0
T88	0	3	0	0
T129	0	6	0	0
T130	0	8	0	0
T131	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	1558	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	16	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	0	0	0
T22	302792	0	0	0
T33	0	5	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	9	0	0
T46	0	28	0	0
T72	2711	0	0	0
T88	0	12	0	0
T128	0	3	0	0
T129	0	3	0	0
T130	0	6	0	0
T132	0	3	0	0
T133	0	1	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24694668	1065	0	0
T11	15167	0	0	0
T12	15077	0	0	0
T13	261585	15	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	124605	0	0	0
T22	302792	2	0	0
T33	0	17	0	0
T34	6503	0	0	0
T35	2708	0	0	0
T36	0	11	0	0
T37	0	2	0	0
T46	0	19	0	0
T72	2711	0	0	0
T88	0	4	0	0
T128	0	8	0	0
T129	0	1	0	0
T130	0	5	0	0