Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72445851	141026	0	0
StatusRise_A	72445851	157401	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72445851	141026	0	0
T1	5868	6	0	0
T2	3831	8	0	0
T3	3801	0	0	0
T4	6246	15	0	0
T5	45972	3	0	0
T6	12234	3	0	0
T7	4548	12	0	0
T8	11220	21	0	0
T9	133221	239	0	0
T10	5229	15	0	0
T13	0	1996	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72445851	157401	0	0
T1	5868	9	0	0
T2	3831	10	0	0
T3	3801	9	0	0
T4	6246	18	0	0
T5	45972	6	0	0
T6	12234	6	0	0
T7	4548	15	0	0
T8	11220	24	0	0
T9	133221	245	0	0
T10	5229	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24148617	52189	0	0
StatusRise_A	24148617	58104	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	52189	0	0
T1	1956	2	0	0
T2	1277	3	0	0
T3	1267	0	0	0
T4	2082	5	0	0
T5	15324	1	0	0
T6	4078	1	0	0
T7	1516	4	0	0
T8	3740	7	0	0
T9	44407	92	0	0
T10	1743	5	0	0
T13	0	726	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	58104	0	0
T1	1956	3	0	0
T2	1277	4	0	0
T3	1267	3	0	0
T4	2082	6	0	0
T5	15324	2	0	0
T6	4078	2	0	0
T7	1516	5	0	0
T8	3740	8	0	0
T9	44407	94	0	0
T10	1743	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24148617	52190	0	0
StatusRise_A	24148617	58104	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	52190	0	0
T1	1956	2	0	0
T2	1277	3	0	0
T3	1267	0	0	0
T4	2082	5	0	0
T5	15324	1	0	0
T6	4078	1	0	0
T7	1516	4	0	0
T8	3740	7	0	0
T9	44407	92	0	0
T10	1743	5	0	0
T13	0	726	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	58104	0	0
T1	1956	3	0	0
T2	1277	4	0	0
T3	1267	3	0	0
T4	2082	6	0	0
T5	15324	2	0	0
T6	4078	2	0	0
T7	1516	5	0	0
T8	3740	8	0	0
T9	44407	94	0	0
T10	1743	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24148617	36647	0	0
StatusRise_A	24148617	41193	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	36647	0	0
T1	1956	2	0	0
T2	1277	2	0	0
T3	1267	0	0	0
T4	2082	5	0	0
T5	15324	1	0	0
T6	4078	1	0	0
T7	1516	4	0	0
T8	3740	7	0	0
T9	44407	55	0	0
T10	1743	5	0	0
T13	0	544	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	41193	0	0
T1	1956	3	0	0
T2	1277	2	0	0
T3	1267	3	0	0
T4	2082	6	0	0
T5	15324	2	0	0
T6	4078	2	0	0
T7	1516	5	0	0
T8	3740	8	0	0
T9	44407	57	0	0
T10	1743	6	0	0