Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24149198	5618	0	0
EscTimeoutStoppedByClReset_A	24148617	3422001	0	0
EscTimeoutTriggersReset_A	4840940	319	0	0
RomAllowActiveState_A	24148617	57698	0	0
RomAllowCheckGoodState_A	24148617	57750	0	0
RomBlockActiveState_A	24148617	29065	0	0
RomBlockCheckGoodState_A	24148617	432402	0	0
RomIntgChkDisFalse_A	24148617	23513213	0	0
RomIntgChkDisTrue_A	24148617	123127	0	0
RstreqChkEsctimeout_A	24148617	4322	0	0
RstreqChkFsmterm_A	24148617	160	0	0
RstreqChkGlbesc_A	24148617	4322	0	0
RstreqChkMainpd_A	24148617	996184	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24149198	5618	0	0
T5	15324	49	0	0
T6	4079	0	0	0
T7	1517	0	0	0
T8	3741	0	0	0
T9	44407	0	0	0
T10	1744	0	0	0
T11	0	56	0	0
T12	0	145	0	0
T13	261586	0	0	0
T14	2888	0	0	0
T20	20714	0	0	0
T21	124606	0	0	0
T95	0	7	0	0
T134	0	39	0	0
T135	0	243	0	0
T136	0	12	0	0
T137	0	28	0	0
T138	0	26	0	0
T139	0	216	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	3422001	0	0
T1	1956	131	0	0
T2	1277	0	0	0
T3	1267	13	0	0
T4	2082	122	0	0
T5	15324	48	0	0
T6	4078	14	0	0
T7	1516	76	0	0
T8	3740	210	0	0
T9	44407	7007	0	0
T10	1743	94	0	0
T13	0	25943	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4840940	319	0	0
T5	481	2	0	0
T6	1161	0	0	0
T7	519	0	0	0
T8	491	0	0	0
T9	6581	0	0	0
T10	891	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	89969	0	0	0
T14	224	0	0	0
T20	9558	0	0	0
T21	44528	0	0	0
T95	0	3	0	0
T134	0	2	0	0
T135	0	3	0	0
T136	0	3	0	0
T137	0	2	0	0
T140	0	3	0	0
T141	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	57698	0	0
T1	1956	3	0	0
T2	1277	4	0	0
T3	1267	3	0	0
T4	2082	6	0	0
T5	15324	2	0	0
T6	4078	2	0	0
T7	1516	5	0	0
T8	3740	8	0	0
T9	44407	94	0	0
T10	1743	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	57750	0	0
T1	1956	3	0	0
T2	1277	4	0	0
T3	1267	3	0	0
T4	2082	6	0	0
T5	15324	2	0	0
T6	4078	2	0	0
T7	1516	5	0	0
T8	3740	8	0	0
T9	44407	94	0	0
T10	1743	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	29065	0	0
T4	2082	255	0	0
T5	15324	0	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	784	0	0
T9	44407	0	0	0
T10	1743	114	0	0
T13	261585	0	0	0
T14	2887	0	0	0
T20	20713	4	0	0
T96	0	252	0	0
T142	0	948	0	0
T143	0	237	0	0
T144	0	2	0	0
T145	0	120	0	0
T146	0	15	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	432402	0	0
T4	2082	68	0	0
T5	15324	0	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	361	0	0
T9	44407	2772	0	0
T10	1743	3	0	0
T13	261585	2269	0	0
T14	2887	0	0	0
T20	20713	1071	0	0
T21	0	1375	0	0
T22	0	712	0	0
T36	0	3743	0	0
T37	0	3462	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	23513213	0	0
T1	1956	1904	0	0
T2	1277	1178	0	0
T3	1267	1016	0	0
T4	2082	1057	0	0
T5	15324	15265	0	0
T6	4078	3981	0	0
T7	1516	1179	0	0
T8	3740	3085	0	0
T9	44407	20958	0	0
T10	1743	680	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	123127	0	0
T4	2082	958	0	0
T5	15324	0	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	556	0	0
T9	44407	23315	0	0
T10	1743	973	0	0
T13	261585	0	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T142	0	455	0	0
T143	0	116	0	0
T144	0	464	0	0
T145	0	68	0	0
T146	0	520	0	0
T147	0	15994	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	4322	0	0
T4	2082	5	0	0
T5	15324	1	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	4	0	0
T9	44407	0	0	0
T10	1743	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	261585	78	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	0	48	0	0
T22	0	67	0	0
T34	0	8	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	160	0	0
T17	17290	40	0	0
T18	0	20	0	0
T19	0	40	0	0
T23	0	20	0	0
T24	0	40	0	0
T25	15170	0	0	0
T26	1825	0	0	0
T27	1252	0	0	0
T28	3222	0	0	0
T29	1196	0	0	0
T30	59782	0	0	0
T31	2771	0	0	0
T32	14744	0	0	0
T33	296121	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	4322	0	0
T4	2082	5	0	0
T5	15324	1	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	4	0	0
T9	44407	0	0	0
T10	1743	3	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	261585	78	0	0
T14	2887	0	0	0
T20	20713	0	0	0
T21	0	48	0	0
T22	0	67	0	0
T34	0	8	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148617	996184	0	0
T1	1956	128	0	0
T2	1277	0	0	0
T3	1267	11	0	0
T4	2082	61	0	0
T5	15324	0	0	0
T6	4078	0	0	0
T7	1516	0	0	0
T8	3740	590	0	0
T9	44407	4527	0	0
T10	1743	52	0	0
T13	0	5009	0	0
T20	0	1563	0	0
T21	0	3358	0	0
T34	0	755	0	0