Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

196782

1

T1

23

T2

31

T3

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	371312	1			T1	65		T2	182		T3	101
values[0x0]	168758	1			T1	28		T2	36		T3	57
values[0x1]	168895	1			T1	34		T2	26		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

303892

1

T1

48

T2

87

T3

99

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2385	1			T4	60		T6	6		T7	5
valid_sources[0x01]	2412	1			T3	5		T4	69		T6	6
valid_sources[0x02]	2700	1			T4	63		T6	3		T34	3
valid_sources[0x03]	4492	1			T3	3		T4	74		T6	10
valid_sources[0x04]	2143	1			T4	46		T6	4		T34	1
valid_sources[0x05]	2424	1			T3	2		T4	56		T6	5
valid_sources[0x06]	2425	1			T3	7		T4	50		T6	1
valid_sources[0x07]	2507	1			T4	46		T6	9		T22	6
valid_sources[0x08]	2167	1			T4	57		T6	5		T14	13
valid_sources[0x09]	3338	1			T4	52		T6	15		T7	5
valid_sources[0x0a]	2451	1			T4	67		T6	9		T8	1
valid_sources[0x0b]	2394	1			T4	56		T6	5		T7	2
valid_sources[0x0c]	3556	1			T4	51		T6	3		T34	1
valid_sources[0x0d]	2218	1			T4	71		T6	4		T8	2
valid_sources[0x0e]	2989	1			T3	1		T4	72		T6	8
valid_sources[0x0f]	5124	1			T4	49		T6	6		T7	3
valid_sources[0x10]	3037	1			T4	58		T6	4		T7	1
valid_sources[0x11]	1930	1			T3	3		T4	63		T6	3
valid_sources[0x12]	3290	1			T4	59		T6	7		T7	3
valid_sources[0x13]	2449	1			T3	1		T4	45		T6	2
valid_sources[0x14]	2173	1			T4	61		T6	13		T7	1
valid_sources[0x15]	3844	1			T4	55		T6	6		T7	3
valid_sources[0x16]	2221	1			T3	1		T4	41		T6	5
valid_sources[0x17]	2309	1			T4	66		T6	10		T8	1
valid_sources[0x18]	2822	1			T4	67		T6	1		T8	1
valid_sources[0x19]	2832	1			T4	52		T6	11		T8	3
valid_sources[0x1a]	2376	1			T3	2		T4	70		T6	9
valid_sources[0x1b]	2121	1			T4	53		T6	2		T7	3
valid_sources[0x1c]	2131	1			T4	61		T6	5		T22	4
valid_sources[0x1d]	3318	1			T4	61		T6	4		T8	2
valid_sources[0x1e]	2163	1			T4	70		T6	19		T22	2
valid_sources[0x1f]	2167	1			T3	1		T4	72		T7	2
valid_sources[0x20]	2153	1			T4	72		T6	8		T8	2
valid_sources[0x21]	2834	1			T4	43		T6	8		T8	2
valid_sources[0x22]	2970	1			T4	53		T6	9		T22	6
valid_sources[0x23]	2382	1			T4	62		T6	6		T22	9
valid_sources[0x24]	4460	1			T3	2		T4	50		T6	4
valid_sources[0x25]	2543	1			T4	63		T6	9		T8	2
valid_sources[0x26]	2350	1			T4	57		T6	3		T34	1
valid_sources[0x27]	2517	1			T4	58		T6	12		T8	1
valid_sources[0x28]	3922	1			T3	1		T4	49		T6	14
valid_sources[0x29]	2097	1			T4	58		T6	9		T8	1
valid_sources[0x2a]	3458	1			T4	68		T6	15		T7	1
valid_sources[0x2b]	3387	1			T4	47		T6	15		T7	7
valid_sources[0x2c]	2976	1			T3	1		T4	73		T6	11
valid_sources[0x2d]	3068	1			T4	48		T6	15		T8	1
valid_sources[0x2e]	2143	1			T4	58		T6	5		T8	2
valid_sources[0x2f]	3559	1			T3	2		T4	48		T6	9
valid_sources[0x30]	2645	1			T3	3		T4	76		T6	22
valid_sources[0x31]	2036	1			T4	68		T6	10		T8	2
valid_sources[0x32]	2471	1			T3	2		T4	76		T8	1
valid_sources[0x33]	2196	1			T4	55		T6	5		T8	1
valid_sources[0x34]	3204	1			T4	54		T6	5		T8	1
valid_sources[0x35]	2534	1			T4	67		T6	12		T34	1
valid_sources[0x36]	2324	1			T4	41		T6	15		T8	1
valid_sources[0x37]	2806	1			T4	67		T6	12		T7	1
valid_sources[0x38]	2057	1			T3	1		T4	65		T6	10
valid_sources[0x39]	2004	1			T3	1		T4	52		T6	8
valid_sources[0x3a]	3341	1			T4	62		T6	7		T8	1
valid_sources[0x3b]	2521	1			T3	2		T4	64		T6	7
valid_sources[0x3c]	2519	1			T4	57		T6	7		T8	2
valid_sources[0x3d]	2506	1			T4	59		T6	13		T8	3
valid_sources[0x3e]	2184	1			T4	37		T6	4		T8	2
valid_sources[0x3f]	4254	1			T4	63		T6	5		T34	2
valid_sources[0x40]	2128	1			T4	65		T6	4		T7	7
valid_sources[0x41]	3075	1			T3	2		T4	67		T6	4
valid_sources[0x42]	5624	1			T3	3		T4	46		T6	6
valid_sources[0x43]	2276	1			T4	56		T6	12		T14	12
valid_sources[0x44]	2706	1			T4	55		T6	19		T8	2
valid_sources[0x45]	6288	1			T4	61		T6	4		T34	2
valid_sources[0x46]	2296	1			T3	2		T4	61		T6	10
valid_sources[0x47]	2139	1			T3	5		T4	57		T6	3
valid_sources[0x48]	2599	1			T3	2		T4	64		T6	7
valid_sources[0x49]	2103	1			T4	54		T6	7		T36	6
valid_sources[0x4a]	2264	1			T3	2		T4	55		T6	11
valid_sources[0x4b]	2414	1			T4	64		T6	2		T14	25
valid_sources[0x4c]	2339	1			T3	2		T4	80		T6	3
valid_sources[0x4d]	2905	1			T4	73		T6	11		T8	1
valid_sources[0x4e]	3650	1			T4	60		T6	2		T22	3
valid_sources[0x4f]	3159	1			T4	64		T6	10		T8	1
valid_sources[0x50]	2283	1			T4	51		T6	19		T8	1
valid_sources[0x51]	2144	1			T3	1		T4	70		T6	10
valid_sources[0x52]	2930	1			T4	55		T6	6		T14	13
valid_sources[0x53]	2376	1			T3	1		T4	82		T6	7
valid_sources[0x54]	2435	1			T4	46		T8	1		T22	3
valid_sources[0x55]	3202	1			T1	127		T3	1		T4	41
valid_sources[0x56]	2088	1			T3	3		T4	77		T6	3
valid_sources[0x57]	2242	1			T4	48		T6	3		T22	3
valid_sources[0x58]	2226	1			T3	1		T4	46		T6	17
valid_sources[0x59]	2512	1			T4	69		T6	7		T8	2
valid_sources[0x5a]	3101	1			T3	3		T4	55		T6	10
valid_sources[0x5b]	2473	1			T4	43		T6	10		T8	1
valid_sources[0x5c]	2129	1			T4	49		T6	9		T8	1
valid_sources[0x5d]	2156	1			T4	44		T6	6		T34	1
valid_sources[0x5e]	2103	1			T3	1		T4	75		T6	3
valid_sources[0x5f]	2235	1			T3	2		T4	61		T6	10
valid_sources[0x60]	3975	1			T4	62		T6	1		T8	1
valid_sources[0x61]	2145	1			T4	69		T34	1		T14	12
valid_sources[0x62]	2415	1			T4	61		T6	2		T14	12
valid_sources[0x63]	2271	1			T3	2		T4	64		T6	16
valid_sources[0x64]	2602	1			T4	49		T6	4		T8	2
valid_sources[0x65]	2138	1			T3	5		T4	67		T6	4
valid_sources[0x66]	2842	1			T4	62		T6	5		T7	3
valid_sources[0x67]	2839	1			T4	56		T6	9		T8	4
valid_sources[0x68]	3995	1			T3	1		T4	65		T6	10
valid_sources[0x69]	2247	1			T4	55		T6	5		T14	13
valid_sources[0x6a]	2815	1			T3	1		T4	41		T6	13
valid_sources[0x6b]	2631	1			T4	49		T6	14		T8	2
valid_sources[0x6c]	2095	1			T3	2		T4	51		T6	4
valid_sources[0x6d]	2214	1			T4	70		T6	3		T8	2
valid_sources[0x6e]	2049	1			T3	6		T4	42		T6	7
valid_sources[0x6f]	3676	1			T4	55		T6	7		T22	1
valid_sources[0x70]	2212	1			T3	2		T4	51		T6	11
valid_sources[0x71]	2238	1			T3	2		T4	45		T6	5
valid_sources[0x72]	2193	1			T4	57		T6	16		T7	2
valid_sources[0x73]	2874	1			T4	54		T6	3		T34	1
valid_sources[0x74]	2972	1			T4	52		T6	9		T8	1
valid_sources[0x75]	2165	1			T3	1		T4	48		T6	7
valid_sources[0x76]	5028	1			T3	5		T4	60		T6	10
valid_sources[0x77]	3620	1			T3	7		T4	57		T6	11
valid_sources[0x78]	3391	1			T3	4		T4	66		T6	6
valid_sources[0x79]	2179	1			T4	70		T6	12		T22	4
valid_sources[0x7a]	2045	1			T4	63		T6	12		T7	3
valid_sources[0x7b]	2252	1			T4	51		T6	3		T14	13
valid_sources[0x7c]	2466	1			T4	47		T6	4		T34	1
valid_sources[0x7d]	3039	1			T3	4		T4	49		T6	3
valid_sources[0x7e]	2497	1			T4	47		T6	3		T8	1
valid_sources[0x7f]	2191	1			T3	5		T4	59		T6	3
valid_sources[0x80]	2983	1			T4	42		T5	861		T6	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

99058

1

T1

10

T2

16

T3

26

values[0x0]

all_enables

biggest_size

63283

1

T1

10

T2

14

T3

21

values[0x1]

all_enables

biggest_size

34441

1

T1

3

T2

1

T3

14