SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35042 | 1 | T5 | 309 | T10 | 314 | T22 | 314 | ||||
others[1] | 35063 | 1 | T5 | 260 | T10 | 307 | T22 | 296 | ||||
others[2] | 34724 | 1 | T5 | 305 | T10 | 284 | T22 | 287 | ||||
others[3] | 58552 | 1 | T5 | 510 | T10 | 487 | T22 | 504 | ||||
false | 18948 | 1 | T3 | 24 | T4 | 368 | T5 | 50 | ||||
true | 29000 | 1 | T1 | 1 | T2 | 1 | T3 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34866 | 1 | T5 | 291 | T10 | 301 | T22 | 304 | ||||
others[1] | 35184 | 1 | T5 | 318 | T10 | 293 | T22 | 281 | ||||
others[2] | 34953 | 1 | T5 | 310 | T10 | 310 | T22 | 293 | ||||
others[3] | 58350 | 1 | T5 | 492 | T10 | 484 | T22 | 506 | ||||
false | 12064 | 1 | T3 | 12 | T4 | 184 | T5 | 50 | ||||
true | 22194 | 1 | T1 | 1 | T2 | 1 | T3 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 738 | 1 | T2 | 6 | T4 | 4 | T6 | 5 | ||||
others[1] | 734 | 1 | T2 | 5 | T4 | 9 | T6 | 1 | ||||
others[2] | 710 | 1 | T2 | 3 | T4 | 9 | T8 | 1 | ||||
others[3] | 1178 | 1 | T2 | 11 | T4 | 16 | T6 | 4 | ||||
false | 14083 | 1 | T1 | 1 | T2 | 4 | T3 | 2 | ||||
true | 4274 | 1 | T4 | 48 | T6 | 9 | T8 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |