Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
32 |
32 |
100.00 |
Total Bits 0->1 |
16 |
16 |
100.00 |
Total Bits 1->0 |
16 |
16 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
32 |
32 |
100.00 |
Port Bits 0->1 |
16 |
16 |
100.00 |
Port Bits 1->0 |
16 |
16 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[3:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[4] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[8:5] |
Yes |
Yes |
*T1,*T3,*T4 |
Yes |
T1,T3,T4 |
INPUT |
oh_i[9] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[11:10] |
Yes |
Yes |
*T18,*T19,*T20 |
Yes |
T18,T19,T20 |
INPUT |
oh_i[13:12] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[15:14] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[16] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T18,T19,T20 |
Yes |
T18,T19,T20 |
OUTPUT |
*Tests covering at least one bit in the range