Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22721128	15871	0	0
intr_enable_rd_A	22721128	30408	0	0
reset_en_rd_A	22721128	2120	0	0
reset_en_regwen_rd_A	22721128	1871	0	0
wake_info_capture_dis_rd_A	22721128	1947	0	0
wakeup_en_rd_A	22721128	3323	0	0
wakeup_en_regwen_rd_A	22721128	1820	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	15871	0	0
T4	565509	131	0	0
T5	23046	0	0	0
T6	52356	0	0	0
T7	10402	0	0	0
T8	7083	0	0	0
T9	7643	0	0	0
T10	21435	0	0	0
T14	206828	3	0	0
T21	0	12	0	0
T25	0	18	0	0
T34	3055	0	0	0
T38	1265	0	0	0
T47	0	11	0	0
T123	0	9	0	0
T124	0	34	0	0
T125	0	11	0	0
T126	0	24	0	0
T127	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	30408	0	0
T3	4402	59	0	0
T4	565509	0	0	0
T5	23046	0	0	0
T6	52356	0	0	0
T7	10402	33	0	0
T8	7083	0	0	0
T9	7643	0	0	0
T10	21435	0	0	0
T14	206828	0	0	0
T34	3055	0	0	0
T36	0	235	0	0
T38	0	13	0	0
T86	0	88	0	0
T128	0	63	0	0
T129	0	85	0	0
T130	0	17	0	0
T131	0	8	0	0
T132	0	67	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	2120	0	0
T48	0	9	0	0
T51	0	13	0	0
T56	0	26	0	0
T61	0	10	0	0
T71	0	21	0	0
T75	0	15	0	0
T77	374498	5	0	0
T96	3311	0	0	0
T97	4754	0	0	0
T133	0	5	0	0
T134	0	20	0	0
T135	0	4	0	0
T136	1934	0	0	0
T137	6973	0	0	0
T138	1920	0	0	0
T139	4264	0	0	0
T140	2809	0	0	0
T141	14373	0	0	0
T142	2432	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	1871	0	0
T48	0	7	0	0
T51	0	12	0	0
T56	0	26	0	0
T61	0	5	0	0
T71	0	5	0	0
T75	0	15	0	0
T77	374498	1	0	0
T96	3311	0	0	0
T97	4754	0	0	0
T134	0	13	0	0
T135	0	9	0	0
T136	1934	0	0	0
T137	6973	0	0	0
T138	1920	0	0	0
T139	4264	0	0	0
T140	2809	0	0	0
T141	14373	0	0	0
T142	2432	0	0	0
T143	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	1947	0	0
T48	0	10	0	0
T51	0	11	0	0
T61	0	2	0	0
T71	0	12	0	0
T75	0	14	0	0
T77	374498	2	0	0
T96	3311	0	0	0
T97	4754	0	0	0
T133	0	1	0	0
T134	0	12	0	0
T135	0	9	0	0
T136	1934	0	0	0
T137	6973	0	0	0
T138	1920	0	0	0
T139	4264	0	0	0
T140	2809	0	0	0
T141	14373	0	0	0
T142	2432	0	0	0
T143	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	3323	0	0
T48	0	2	0	0
T51	0	14	0	0
T61	0	31	0	0
T71	0	47	0	0
T75	0	2	0	0
T77	374498	6	0	0
T96	3311	0	0	0
T97	4754	0	0	0
T133	0	5	0	0
T134	0	18	0	0
T135	0	8	0	0
T136	1934	0	0	0
T137	6973	0	0	0
T138	1920	0	0	0
T139	4264	0	0	0
T140	2809	0	0	0
T141	14373	0	0	0
T142	2432	0	0	0
T143	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22721128	1820	0	0
T48	0	3	0	0
T51	0	3	0	0
T56	0	26	0	0
T61	0	4	0	0
T71	0	14	0	0
T75	0	4	0	0
T77	374498	5	0	0
T96	3311	0	0	0
T97	4754	0	0	0
T133	0	2	0	0
T134	0	24	0	0
T135	0	9	0	0
T136	1934	0	0	0
T137	6973	0	0	0
T138	1920	0	0	0
T139	4264	0	0	0
T140	2809	0	0	0
T141	14373	0	0	0
T142	2432	0	0	0