Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66168804	144242	0	0
StatusRise_A	66168804	161128	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66168804	144242	0	0
T1	6231	23	0	0
T2	9342	0	0	0
T3	13206	56	0	0
T4	1696527	2480	0	0
T5	69138	215	0	0
T6	157068	312	0	0
T7	31206	26	0	0
T8	21249	72	0	0
T9	22929	54	0	0
T10	64305	219	0	0
T34	0	24	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66168804	161128	0	0
T1	6231	26	0	0
T2	9342	3	0	0
T3	13206	61	0	0
T4	1696527	2769	0	0
T5	69138	220	0	0
T6	157068	345	0	0
T7	31206	28	0	0
T8	21249	78	0	0
T9	22929	60	0	0
T10	64305	225	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22056268	53538	0	0
StatusRise_A	22056268	59622	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	53538	0	0
T1	2077	9	0	0
T2	3114	0	0	0
T3	4402	23	0	0
T4	565509	913	0	0
T5	23046	84	0	0
T6	52356	112	0	0
T7	10402	9	0	0
T8	7083	24	0	0
T9	7643	18	0	0
T10	21435	90	0	0
T34	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	59622	0	0
T1	2077	10	0	0
T2	3114	1	0	0
T3	4402	25	0	0
T4	565509	1019	0	0
T5	23046	86	0	0
T6	52356	124	0	0
T7	10402	10	0	0
T8	7083	26	0	0
T9	7643	20	0	0
T10	21435	92	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22056268	53538	0	0
StatusRise_A	22056268	59622	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	53538	0	0
T1	2077	9	0	0
T2	3114	0	0	0
T3	4402	23	0	0
T4	565509	913	0	0
T5	23046	84	0	0
T6	52356	112	0	0
T7	10402	9	0	0
T8	7083	24	0	0
T9	7643	18	0	0
T10	21435	90	0	0
T34	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	59622	0	0
T1	2077	10	0	0
T2	3114	1	0	0
T3	4402	25	0	0
T4	565509	1019	0	0
T5	23046	86	0	0
T6	52356	124	0	0
T7	10402	10	0	0
T8	7083	26	0	0
T9	7643	20	0	0
T10	21435	92	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22056268	37166	0	0
StatusRise_A	22056268	41884	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	37166	0	0
T1	2077	5	0	0
T2	3114	0	0	0
T3	4402	10	0	0
T4	565509	654	0	0
T5	23046	47	0	0
T6	52356	88	0	0
T7	10402	8	0	0
T8	7083	24	0	0
T9	7643	18	0	0
T10	21435	39	0	0
T34	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	41884	0	0
T1	2077	6	0	0
T2	3114	1	0	0
T3	4402	11	0	0
T4	565509	731	0	0
T5	23046	48	0	0
T6	52356	97	0	0
T7	10402	8	0	0
T8	7083	26	0	0
T9	7643	20	0	0
T10	21435	41	0	0