Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	22056838	6036	0	0
EscTimeoutStoppedByClReset_A	22056268	2980746	0	0
EscTimeoutTriggersReset_A	5193009	314	0	0
RomAllowActiveState_A	22056268	59213	0	0
RomAllowCheckGoodState_A	22056268	59263	0	0
RomBlockActiveState_A	22056268	31271	0	0
RomBlockCheckGoodState_A	22056268	421593	0	0
RomIntgChkDisFalse_A	22056268	21450370	0	0
RomIntgChkDisTrue_A	22056268	80268	0	0
RstreqChkEsctimeout_A	22056268	4742	0	0
RstreqChkFsmterm_A	22056268	180	0	0
RstreqChkGlbesc_A	22056268	4742	0	0
RstreqChkMainpd_A	22056268	922116	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056838	6036	0	0
T11	15810	259	0	0
T12	0	34	0	0
T13	0	10	0	0
T26	0	4	0	0
T43	7575	0	0	0
T44	2830	0	0	0
T46	16426	0	0	0
T47	62495	0	0	0
T58	4073	0	0	0
T88	61469	0	0	0
T89	2748	0	0	0
T90	55328	0	0	0
T91	1366	0	0	0
T144	0	146	0	0
T145	0	10	0	0
T146	0	34	0	0
T147	0	244	0	0
T148	0	145	0	0
T149	0	139	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	2980746	0	0
T1	2077	279	0	0
T2	3114	0	0	0
T3	4402	204	0	0
T4	565509	102531	0	0
T5	23046	3607	0	0
T6	52356	11148	0	0
T7	10402	803	0	0
T8	7083	1186	0	0
T9	7643	235	0	0
T10	21435	2416	0	0
T34	0	312	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5193009	314	0	0
T11	203	3	0	0
T12	0	3	0	0
T13	0	3	0	0
T26	0	5	0	0
T43	724	0	0	0
T44	293	0	0	0
T46	7558	0	0	0
T47	27810	0	0	0
T58	1606	0	0	0
T88	22144	0	0	0
T89	249	0	0	0
T90	5929	0	0	0
T91	358	0	0	0
T144	0	3	0	0
T145	0	5	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	59213	0	0
T1	2077	10	0	0
T2	3114	1	0	0
T3	4402	25	0	0
T4	565509	1019	0	0
T5	23046	86	0	0
T6	52356	124	0	0
T7	10402	10	0	0
T8	7083	26	0	0
T9	7643	13	0	0
T10	21435	92	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	59263	0	0
T1	2077	10	0	0
T2	3114	1	0	0
T3	4402	25	0	0
T4	565509	1019	0	0
T5	23046	86	0	0
T6	52356	124	0	0
T7	10402	10	0	0
T8	7083	26	0	0
T9	7643	14	0	0
T10	21435	92	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	31271	0	0
T5	23046	16	0	0
T6	52356	0	0	0
T7	10402	0	0	0
T8	7083	0	0	0
T9	7643	0	0	0
T10	21435	2	0	0
T14	206828	0	0	0
T22	56109	0	0	0
T34	3055	0	0	0
T38	1265	0	0	0
T46	0	17	0	0
T150	0	304	0	0
T151	0	917	0	0
T152	0	9	0	0
T153	0	19	0	0
T154	0	577	0	0
T155	0	1240	0	0
T156	0	1442	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	421593	0	0
T3	4402	275	0	0
T4	565509	4223	0	0
T5	23046	1454	0	0
T6	52356	321	0	0
T7	10402	0	0	0
T8	7083	0	0	0
T9	7643	0	0	0
T10	21435	1340	0	0
T14	206828	2911	0	0
T22	0	4086	0	0
T34	3055	0	0	0
T36	0	296	0	0
T157	0	92	0	0
T158	0	4025	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	21450370	0	0
T1	2077	2000	0	0
T2	3114	3029	0	0
T3	4402	4232	0	0
T4	565509	557450	0	0
T5	23046	22406	0	0
T6	52356	51391	0	0
T7	10402	10333	0	0
T8	7083	6921	0	0
T9	7643	6541	0	0
T10	21435	21141	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	80268	0	0
T5	23046	496	0	0
T6	52356	0	0	0
T7	10402	0	0	0
T8	7083	0	0	0
T9	7643	0	0	0
T10	21435	142	0	0
T14	206828	0	0	0
T22	56109	2099	0	0
T34	3055	0	0	0
T38	1265	0	0	0
T46	0	264	0	0
T150	0	580	0	0
T151	0	1253	0	0
T152	0	232	0	0
T158	0	1612	0	0
T159	0	862	0	0
T160	0	1084	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	4742	0	0
T4	565509	66	0	0
T5	23046	0	0	0
T6	52356	12	0	0
T7	10402	0	0	0
T8	7083	10	0	0
T9	7643	6	0	0
T10	21435	0	0	0
T14	206828	40	0	0
T34	3055	2	0	0
T35	0	3	0	0
T36	0	12	0	0
T38	1265	0	0	0
T39	0	4	0	0
T40	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	180	0	0
T18	17305	40	0	0
T19	0	20	0	0
T20	0	40	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	294323	0	0	0
T26	821	0	0	0
T27	5055	0	0	0
T28	14981	0	0	0
T29	3391	0	0	0
T30	55328	0	0	0
T31	2288	0	0	0
T32	17239	0	0	0
T33	3543	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	4742	0	0
T4	565509	66	0	0
T5	23046	0	0	0
T6	52356	12	0	0
T7	10402	0	0	0
T8	7083	10	0	0
T9	7643	6	0	0
T10	21435	0	0	0
T14	206828	40	0	0
T34	3055	2	0	0
T35	0	3	0	0
T36	0	12	0	0
T38	1265	0	0	0
T39	0	4	0	0
T40	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22056268	922116	0	0
T3	4402	501	0	0
T4	565509	25208	0	0
T5	23046	2023	0	0
T6	52356	2079	0	0
T7	10402	0	0	0
T8	7083	1206	0	0
T9	7643	117	0	0
T10	21435	1929	0	0
T14	206828	5578	0	0
T22	0	6554	0	0
T34	3055	347	0	0