Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12894 |
1 |
|
|
T2 |
32 |
|
T5 |
8 |
|
T8 |
1 |
auto[1] |
15899 |
1 |
|
|
T2 |
18 |
|
T5 |
11 |
|
T8 |
2 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13638 |
1 |
|
|
T2 |
19 |
|
T5 |
8 |
|
T9 |
3 |
auto[1] |
15155 |
1 |
|
|
T2 |
31 |
|
T5 |
11 |
|
T8 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1736 |
1 |
|
|
T61 |
1 |
|
T90 |
1 |
|
T64 |
3 |
auto[0] |
auto[0] |
auto[1] |
1762 |
1 |
|
|
T8 |
1 |
|
T60 |
2 |
|
T61 |
1 |
auto[0] |
auto[1] |
auto[0] |
4917 |
1 |
|
|
T2 |
12 |
|
T5 |
3 |
|
T9 |
2 |
auto[0] |
auto[1] |
auto[1] |
4479 |
1 |
|
|
T2 |
20 |
|
T5 |
5 |
|
T9 |
3 |
auto[1] |
auto[0] |
auto[0] |
1896 |
1 |
|
|
T60 |
1 |
|
T61 |
1 |
|
T64 |
2 |
auto[1] |
auto[0] |
auto[1] |
2468 |
1 |
|
|
T8 |
1 |
|
T60 |
2 |
|
T61 |
5 |
auto[1] |
auto[1] |
auto[0] |
5089 |
1 |
|
|
T2 |
7 |
|
T5 |
5 |
|
T9 |
1 |
auto[1] |
auto[1] |
auto[1] |
6446 |
1 |
|
|
T2 |
11 |
|
T5 |
6 |
|
T8 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13084 |
1 |
|
|
T2 |
20 |
|
T5 |
10 |
|
T9 |
2 |
auto[1] |
15709 |
1 |
|
|
T2 |
30 |
|
T5 |
9 |
|
T8 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13780 |
1 |
|
|
T2 |
28 |
|
T5 |
11 |
|
T8 |
3 |
auto[1] |
15013 |
1 |
|
|
T2 |
22 |
|
T5 |
8 |
|
T9 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1832 |
1 |
|
|
T60 |
2 |
|
T61 |
2 |
|
T90 |
2 |
auto[0] |
auto[0] |
auto[1] |
1870 |
1 |
|
|
T60 |
1 |
|
T61 |
2 |
|
T64 |
3 |
auto[0] |
auto[1] |
auto[0] |
4925 |
1 |
|
|
T2 |
11 |
|
T5 |
6 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[1] |
4457 |
1 |
|
|
T2 |
9 |
|
T5 |
4 |
|
T9 |
1 |
auto[1] |
auto[0] |
auto[0] |
1844 |
1 |
|
|
T8 |
2 |
|
T60 |
1 |
|
T61 |
4 |
auto[1] |
auto[0] |
auto[1] |
2316 |
1 |
|
|
T60 |
1 |
|
T64 |
3 |
|
T47 |
11 |
auto[1] |
auto[1] |
auto[0] |
5179 |
1 |
|
|
T2 |
17 |
|
T5 |
5 |
|
T8 |
1 |
auto[1] |
auto[1] |
auto[1] |
6370 |
1 |
|
|
T2 |
13 |
|
T5 |
4 |
|
T9 |
2 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12914 |
1 |
|
|
T2 |
18 |
|
T5 |
12 |
|
T9 |
6 |
auto[1] |
15879 |
1 |
|
|
T2 |
32 |
|
T5 |
7 |
|
T8 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13625 |
1 |
|
|
T2 |
23 |
|
T5 |
7 |
|
T8 |
2 |
auto[1] |
15168 |
1 |
|
|
T2 |
27 |
|
T5 |
12 |
|
T8 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1817 |
1 |
|
|
T60 |
2 |
|
T61 |
1 |
|
T47 |
5 |
auto[0] |
auto[0] |
auto[1] |
1807 |
1 |
|
|
T60 |
1 |
|
T61 |
3 |
|
T64 |
4 |
auto[0] |
auto[1] |
auto[0] |
4862 |
1 |
|
|
T2 |
7 |
|
T5 |
6 |
|
T9 |
3 |
auto[0] |
auto[1] |
auto[1] |
4428 |
1 |
|
|
T2 |
11 |
|
T5 |
6 |
|
T9 |
3 |
auto[1] |
auto[0] |
auto[0] |
1771 |
1 |
|
|
T8 |
1 |
|
T60 |
1 |
|
T64 |
1 |
auto[1] |
auto[0] |
auto[1] |
2467 |
1 |
|
|
T8 |
1 |
|
T60 |
1 |
|
T61 |
4 |
auto[1] |
auto[1] |
auto[0] |
5175 |
1 |
|
|
T2 |
16 |
|
T5 |
1 |
|
T8 |
1 |
auto[1] |
auto[1] |
auto[1] |
6466 |
1 |
|
|
T2 |
16 |
|
T5 |
6 |
|
T25 |
15 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13060 |
1 |
|
|
T2 |
30 |
|
T5 |
8 |
|
T9 |
2 |
auto[1] |
15733 |
1 |
|
|
T2 |
20 |
|
T5 |
11 |
|
T8 |
3 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13717 |
1 |
|
|
T2 |
27 |
|
T5 |
11 |
|
T8 |
3 |
auto[1] |
15076 |
1 |
|
|
T2 |
23 |
|
T5 |
8 |
|
T9 |
4 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1885 |
1 |
|
|
T61 |
2 |
|
T90 |
1 |
|
T47 |
7 |
auto[0] |
auto[0] |
auto[1] |
1774 |
1 |
|
|
T60 |
1 |
|
T61 |
2 |
|
T64 |
3 |
auto[0] |
auto[1] |
auto[0] |
4926 |
1 |
|
|
T2 |
20 |
|
T5 |
4 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[1] |
4475 |
1 |
|
|
T2 |
10 |
|
T5 |
4 |
|
T9 |
1 |
auto[1] |
auto[0] |
auto[0] |
1756 |
1 |
|
|
T8 |
2 |
|
T60 |
3 |
|
T64 |
2 |
auto[1] |
auto[0] |
auto[1] |
2447 |
1 |
|
|
T60 |
1 |
|
T61 |
4 |
|
T90 |
1 |
auto[1] |
auto[1] |
auto[0] |
5150 |
1 |
|
|
T2 |
7 |
|
T5 |
7 |
|
T8 |
1 |
auto[1] |
auto[1] |
auto[1] |
6380 |
1 |
|
|
T2 |
13 |
|
T5 |
4 |
|
T9 |
3 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12954 |
1 |
|
|
T2 |
28 |
|
T5 |
4 |
|
T8 |
2 |
auto[1] |
15839 |
1 |
|
|
T2 |
22 |
|
T5 |
15 |
|
T8 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13728 |
1 |
|
|
T2 |
27 |
|
T5 |
8 |
|
T8 |
2 |
auto[1] |
15065 |
1 |
|
|
T2 |
23 |
|
T5 |
11 |
|
T8 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1854 |
1 |
|
|
T60 |
1 |
|
T61 |
1 |
|
T64 |
3 |
auto[0] |
auto[0] |
auto[1] |
1808 |
1 |
|
|
T8 |
1 |
|
T60 |
1 |
|
T61 |
1 |
auto[0] |
auto[1] |
auto[0] |
4856 |
1 |
|
|
T2 |
18 |
|
T5 |
2 |
|
T8 |
1 |
auto[0] |
auto[1] |
auto[1] |
4436 |
1 |
|
|
T2 |
10 |
|
T5 |
2 |
|
T25 |
9 |
auto[1] |
auto[0] |
auto[0] |
1777 |
1 |
|
|
T8 |
1 |
|
T60 |
1 |
|
T61 |
3 |
auto[1] |
auto[0] |
auto[1] |
2423 |
1 |
|
|
T60 |
2 |
|
T61 |
3 |
|
T90 |
1 |
auto[1] |
auto[1] |
auto[0] |
5241 |
1 |
|
|
T2 |
9 |
|
T5 |
6 |
|
T9 |
4 |
auto[1] |
auto[1] |
auto[1] |
6398 |
1 |
|
|
T2 |
13 |
|
T5 |
9 |
|
T9 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7862 |
1 |
|
|
T8 |
2 |
|
T60 |
5 |
|
T61 |
8 |
auto[1] |
20931 |
1 |
|
|
T2 |
50 |
|
T5 |
19 |
|
T8 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12942 |
1 |
|
|
T2 |
25 |
|
T5 |
9 |
|
T8 |
2 |
auto[1] |
15851 |
1 |
|
|
T2 |
25 |
|
T5 |
10 |
|
T8 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13613 |
1 |
|
|
T2 |
29 |
|
T5 |
4 |
|
T8 |
2 |
auto[1] |
15180 |
1 |
|
|
T2 |
21 |
|
T5 |
15 |
|
T8 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1792 |
1 |
|
|
T8 |
2 |
|
T60 |
2 |
|
T61 |
1 |
auto[0] |
auto[0] |
auto[1] |
1809 |
1 |
|
|
T61 |
2 |
|
T64 |
1 |
|
T47 |
5 |
auto[0] |
auto[1] |
auto[0] |
4824 |
1 |
|
|
T2 |
13 |
|
T5 |
3 |
|
T9 |
1 |
auto[0] |
auto[1] |
auto[1] |
4517 |
1 |
|
|
T2 |
12 |
|
T5 |
6 |
|
T9 |
2 |
auto[1] |
auto[0] |
auto[0] |
1776 |
1 |
|
|
T61 |
3 |
|
T90 |
1 |
|
T64 |
3 |
auto[1] |
auto[0] |
auto[1] |
2485 |
1 |
|
|
T60 |
3 |
|
T61 |
2 |
|
T90 |
1 |
auto[1] |
auto[1] |
auto[0] |
5221 |
1 |
|
|
T2 |
16 |
|
T5 |
1 |
|
T9 |
1 |
auto[1] |
auto[1] |
auto[1] |
6369 |
1 |
|
|
T2 |
9 |
|
T5 |
9 |
|
T8 |
1 |