Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	537375	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203871

1

T2

189

T3

29

T5

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	387334	1			T1	1		T2	407		T3	41
values[0x0]	176750	1			T2	226		T3	23		T5	88
values[0x1]	177162	1			T2	226		T3	10		T5	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	425176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

316070

1

T1

1

T2

344

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2428	1			T60	2		T38	1		T64	4
valid_sources[0x01]	4016	1			T37	4		T13	1		T106	1
valid_sources[0x02]	2826	1			T37	3		T106	2		T60	1
valid_sources[0x03]	2422	1			T3	1		T38	5		T64	2
valid_sources[0x04]	10309	1			T37	3		T13	2		T60	1
valid_sources[0x05]	2510	1			T3	1		T13	1		T106	1
valid_sources[0x06]	3439	1			T37	1		T106	1		T60	2
valid_sources[0x07]	3393	1			T37	9		T106	2		T38	2
valid_sources[0x08]	3548	1			T37	11		T13	1		T106	4
valid_sources[0x09]	2649	1			T3	2		T37	4		T106	1
valid_sources[0x0a]	3235	1			T106	1		T60	1		T38	3
valid_sources[0x0b]	3247	1			T37	7		T13	1		T60	3
valid_sources[0x0c]	2366	1			T3	1		T37	8		T60	2
valid_sources[0x0d]	3008	1			T37	4		T38	5		T64	1
valid_sources[0x0e]	3076	1			T13	2		T106	1		T60	3
valid_sources[0x0f]	2538	1			T3	1		T38	3		T15	7
valid_sources[0x10]	2925	1			T37	3		T60	1		T38	2
valid_sources[0x11]	2454	1			T13	3		T14	2		T38	3
valid_sources[0x12]	2511	1			T60	1		T14	1		T38	2
valid_sources[0x13]	2504	1			T37	15		T60	1		T14	1
valid_sources[0x14]	2217	1			T37	2		T60	1		T38	5
valid_sources[0x15]	2341	1			T6	15		T37	18		T38	1
valid_sources[0x16]	2934	1			T37	1		T14	2		T38	3
valid_sources[0x17]	2390	1			T3	1		T37	11		T13	1
valid_sources[0x18]	2426	1			T37	5		T13	2		T106	1
valid_sources[0x19]	3121	1			T14	2		T38	6		T64	2
valid_sources[0x1a]	2499	1			T3	1		T106	2		T14	2
valid_sources[0x1b]	2370	1			T3	1		T37	2		T13	3
valid_sources[0x1c]	3282	1			T37	3		T38	6		T47	17
valid_sources[0x1d]	2724	1			T14	5		T38	2		T47	7
valid_sources[0x1e]	4631	1			T38	2		T64	2		T47	15
valid_sources[0x1f]	2500	1			T37	4		T106	2		T60	1
valid_sources[0x20]	2429	1			T37	5		T106	4		T60	2
valid_sources[0x21]	2938	1			T13	1		T106	3		T60	1
valid_sources[0x22]	3301	1			T60	1		T14	8		T38	8
valid_sources[0x23]	3071	1			T106	2		T60	1		T14	4
valid_sources[0x24]	2657	1			T37	4		T106	1		T14	1
valid_sources[0x25]	2387	1			T37	4		T13	2		T106	1
valid_sources[0x26]	2332	1			T3	1		T13	1		T106	1
valid_sources[0x27]	2384	1			T8	16		T37	22		T60	2
valid_sources[0x28]	3065	1			T3	1		T106	1		T14	1
valid_sources[0x29]	2509	1			T37	3		T60	2		T38	3
valid_sources[0x2a]	3454	1			T13	2		T106	1		T14	4
valid_sources[0x2b]	2684	1			T60	1		T14	1		T38	3
valid_sources[0x2c]	3966	1			T37	2		T13	1		T106	3
valid_sources[0x2d]	2646	1			T3	1		T37	6		T13	1
valid_sources[0x2e]	2582	1			T37	4		T60	1		T38	4
valid_sources[0x2f]	4158	1			T13	1		T106	1		T60	1
valid_sources[0x30]	2495	1			T37	8		T38	5		T15	4
valid_sources[0x31]	2699	1			T37	6		T106	1		T14	2
valid_sources[0x32]	2340	1			T8	2		T37	3		T60	2
valid_sources[0x33]	2446	1			T8	3		T13	1		T106	1
valid_sources[0x34]	2973	1			T60	1		T14	4		T38	3
valid_sources[0x35]	4115	1			T37	7		T13	2		T14	2
valid_sources[0x36]	2419	1			T37	2		T60	1		T14	2
valid_sources[0x37]	2849	1			T3	1		T37	13		T106	2
valid_sources[0x38]	2514	1			T106	1		T14	1		T38	3
valid_sources[0x39]	3201	1			T37	3		T13	1		T106	2
valid_sources[0x3a]	2554	1			T37	5		T106	1		T14	2
valid_sources[0x3b]	2364	1			T3	1		T60	3		T14	1
valid_sources[0x3c]	2700	1			T37	4		T13	1		T106	3
valid_sources[0x3d]	2509	1			T37	1		T13	1		T106	2
valid_sources[0x3e]	2683	1			T3	1		T37	1		T60	1
valid_sources[0x3f]	2796	1			T37	4		T106	3		T60	1
valid_sources[0x40]	2590	1			T6	1		T37	2		T106	2
valid_sources[0x41]	2385	1			T37	8		T106	1		T60	1
valid_sources[0x42]	2239	1			T3	1		T8	11		T37	3
valid_sources[0x43]	3325	1			T37	5		T13	2		T106	1
valid_sources[0x44]	3971	1			T37	1		T13	2		T106	1
valid_sources[0x45]	3064	1			T106	3		T60	1		T38	3
valid_sources[0x46]	3269	1			T25	865		T37	4		T106	2
valid_sources[0x47]	3872	1			T37	8		T14	1		T38	4
valid_sources[0x48]	3097	1			T106	1		T60	1		T14	1
valid_sources[0x49]	4123	1			T37	2		T60	1		T38	9
valid_sources[0x4a]	4289	1			T3	1		T37	5		T13	2
valid_sources[0x4b]	3518	1			T106	5		T14	1		T38	6
valid_sources[0x4c]	2725	1			T3	1		T8	1		T14	2
valid_sources[0x4d]	3227	1			T37	15		T106	2		T38	7
valid_sources[0x4e]	2517	1			T8	2		T37	3		T13	1
valid_sources[0x4f]	3121	1			T37	2		T13	1		T106	1
valid_sources[0x50]	2618	1			T3	1		T37	5		T38	7
valid_sources[0x51]	2258	1			T3	1		T106	1		T14	3
valid_sources[0x52]	6871	1			T37	3		T13	2		T106	1
valid_sources[0x53]	2350	1			T60	1		T14	2		T38	1
valid_sources[0x54]	2489	1			T37	4		T60	2		T14	1
valid_sources[0x55]	2449	1			T3	1		T106	1		T38	3
valid_sources[0x56]	4163	1			T3	1		T37	1		T106	2
valid_sources[0x57]	2306	1			T37	7		T13	1		T60	1
valid_sources[0x58]	2325	1			T37	9		T13	1		T106	1
valid_sources[0x59]	3180	1			T60	1		T14	3		T38	5
valid_sources[0x5a]	2442	1			T37	7		T13	3		T60	2
valid_sources[0x5b]	2652	1			T37	2		T13	1		T14	1
valid_sources[0x5c]	2627	1			T3	1		T37	3		T13	3
valid_sources[0x5d]	2561	1			T37	2		T13	1		T60	1
valid_sources[0x5e]	2524	1			T37	1		T106	4		T14	2
valid_sources[0x5f]	2244	1			T37	3		T60	1		T14	1
valid_sources[0x60]	3710	1			T13	1		T106	3		T60	2
valid_sources[0x61]	2360	1			T37	1		T106	3		T60	1
valid_sources[0x62]	9568	1			T37	1		T38	4		T15	3
valid_sources[0x63]	2548	1			T106	1		T38	4		T47	19
valid_sources[0x64]	2436	1			T3	1		T37	2		T60	1
valid_sources[0x65]	2647	1			T60	1		T38	2		T64	2
valid_sources[0x66]	2740	1			T37	4		T106	2		T14	2
valid_sources[0x67]	2398	1			T37	1		T38	4		T64	2
valid_sources[0x68]	3351	1			T37	4		T13	2		T14	3
valid_sources[0x69]	8276	1			T37	2		T106	1		T14	1
valid_sources[0x6a]	2430	1			T13	1		T14	2		T38	7
valid_sources[0x6b]	2500	1			T106	1		T14	2		T38	2
valid_sources[0x6c]	2270	1			T3	1		T37	5		T106	1
valid_sources[0x6d]	3812	1			T3	1		T37	2		T13	1
valid_sources[0x6e]	2601	1			T37	1		T13	1		T38	4
valid_sources[0x6f]	2371	1			T37	1		T60	2		T14	2
valid_sources[0x70]	2611	1			T3	1		T13	2		T106	1
valid_sources[0x71]	4020	1			T37	14		T60	1		T14	3
valid_sources[0x72]	2237	1			T3	1		T37	1		T106	4
valid_sources[0x73]	2466	1			T106	2		T14	2		T38	3
valid_sources[0x74]	2482	1			T3	1		T37	27		T106	2
valid_sources[0x75]	2338	1			T6	5		T8	5		T37	1
valid_sources[0x76]	2560	1			T3	1		T14	1		T38	4
valid_sources[0x77]	2438	1			T37	6		T106	1		T14	2
valid_sources[0x78]	2318	1			T37	6		T106	2		T38	1
valid_sources[0x79]	2329	1			T37	6		T13	1		T106	1
valid_sources[0x7a]	2372	1			T3	2		T13	1		T38	2
valid_sources[0x7b]	4811	1			T37	2		T13	1		T106	1
valid_sources[0x7c]	3163	1			T106	1		T60	1		T38	4
valid_sources[0x7d]	3209	1			T14	3		T38	3		T47	8
valid_sources[0x7e]	4447	1			T6	1		T37	2		T106	1
valid_sources[0x7f]	2541	1			T3	1		T37	6		T106	1
valid_sources[0x80]	2487	1			T13	1		T106	2		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

102635

1

T2

78

T3

18

T5

33

values[0x0]

all_enables

biggest_size

65796

1

T2

73

T3

10

T5

28

values[0x1]

all_enables

biggest_size

35440

1

T2

38

T3

1

T5

14