SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34945 | 1 | T2 | 298 | T6 | 1 | T25 | 302 | ||||
others[1] | 34850 | 1 | T2 | 306 | T25 | 314 | T37 | 303 | ||||
others[2] | 34918 | 1 | T2 | 285 | T25 | 302 | T37 | 285 | ||||
others[3] | 58757 | 1 | T2 | 505 | T6 | 1 | T25 | 494 | ||||
false | 19937 | 1 | T2 | 50 | T5 | 38 | T6 | 4 | ||||
true | 30258 | 1 | T1 | 3 | T2 | 52 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35035 | 1 | T2 | 281 | T25 | 297 | T37 | 325 | ||||
others[1] | 34848 | 1 | T2 | 296 | T25 | 296 | T37 | 278 | ||||
others[2] | 34995 | 1 | T2 | 282 | T25 | 295 | T37 | 274 | ||||
others[3] | 58787 | 1 | T2 | 545 | T25 | 514 | T37 | 516 | ||||
false | 12572 | 1 | T2 | 50 | T5 | 19 | T6 | 3 | ||||
true | 22950 | 1 | T1 | 3 | T2 | 52 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 696 | 1 | T3 | 2 | T6 | 1 | T106 | 6 | ||||
others[1] | 720 | 1 | T7 | 1 | T106 | 3 | T40 | 2 | ||||
others[2] | 752 | 1 | T6 | 1 | T106 | 4 | T39 | 1 | ||||
others[3] | 1224 | 1 | T7 | 2 | T106 | 15 | T39 | 1 | ||||
false | 14327 | 1 | T1 | 3 | T2 | 2 | T3 | 22 | ||||
true | 4235 | 1 | T3 | 8 | T6 | 3 | T7 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |