Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T25

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	25836650	6448	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	25836650	274363	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	25836650	10657633	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	25836650	274379	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	25836650	6448	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	25836650	274363	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	25836650	10657633	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	25836650	274379	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	6448	0	0
T2	8588	24	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	7	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	3	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	18	0	0
T37	0	24	0	0
T38	0	17	0	0
T43	0	16	0	0
T47	0	37	0	0
T52	0	23	0	0
T67	0	18	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	274363	0	0
T2	8588	390	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	235	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	53	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	1297	0	0
T37	0	337	0	0
T38	0	869	0	0
T43	0	351	0	0
T47	0	1072	0	0
T52	0	491	0	0
T67	0	1019	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	10657633	0	0
T2	8588	4338	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	2908	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	1847	0	0
T9	2897	1017	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T13	0	1189	0	0
T14	0	769	0	0
T25	0	25056	0	0
T37	0	4242	0	0
T38	0	15493	0	0
T60	0	2109	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	274379	0	0
T2	8588	390	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	235	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	53	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	1297	0	0
T37	0	337	0	0
T38	0	869	0	0
T43	0	351	0	0
T47	0	1072	0	0
T52	0	491	0	0
T67	0	1019	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	6448	0	0
T2	8588	24	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	7	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	3	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	18	0	0
T37	0	24	0	0
T38	0	17	0	0
T43	0	16	0	0
T47	0	37	0	0
T52	0	23	0	0
T67	0	18	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	274363	0	0
T2	8588	390	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	235	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	53	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	1297	0	0
T37	0	337	0	0
T38	0	869	0	0
T43	0	351	0	0
T47	0	1072	0	0
T52	0	491	0	0
T67	0	1019	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	10657633	0	0
T2	8588	4338	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	2908	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	1847	0	0
T9	2897	1017	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T13	0	1189	0	0
T14	0	769	0	0
T25	0	25056	0	0
T37	0	4242	0	0
T38	0	15493	0	0
T60	0	2109	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	274379	0	0
T2	8588	390	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	235	0	0
T6	2565	0	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	53	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	1297	0	0
T37	0	337	0	0
T38	0	869	0	0
T43	0	351	0	0
T47	0	1072	0	0
T52	0	491	0	0
T67	0	1019	0	0