Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26336342	14114	0	0
intr_enable_rd_A	26336342	39730	0	0
reset_en_rd_A	26336342	1455	0	0
reset_en_regwen_rd_A	26336342	1234	0	0
wake_info_capture_dis_rd_A	26336342	1230	0	0
wakeup_en_rd_A	26336342	2522	0	0
wakeup_en_regwen_rd_A	26336342	1142	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	14114	0	0
T22	301842	27	0	0
T23	0	17	0	0
T24	0	12	0	0
T56	0	23	0	0
T95	17733	0	0	0
T96	11949	0	0	0
T97	2343	0	0	0
T98	22354	0	0	0
T99	18304	0	0	0
T100	4716	0	0	0
T101	5714	0	0	0
T102	1728	0	0	0
T103	1051	0	0	0
T137	0	33	0	0
T138	0	21	0	0
T139	0	15	0	0
T140	0	2	0	0
T141	0	21	0	0
T142	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	39730	0	0
T8	3122	9	0	0
T9	2897	0	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T13	3263	43	0	0
T14	2322	0	0	0
T15	0	66	0	0
T25	54250	0	0	0
T37	9002	0	0	0
T38	0	150	0	0
T60	4202	0	0	0
T67	0	141	0	0
T96	0	60	0	0
T99	0	33	0	0
T106	3108	0	0	0
T143	0	3	0	0
T144	0	81	0	0
T145	0	27	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	1455	0	0
T70	0	11	0	0
T86	0	7	0	0
T91	0	9	0	0
T138	254507	6	0	0
T141	0	10	0	0
T146	0	5	0	0
T147	0	10	0	0
T148	0	10	0	0
T149	0	15	0	0
T150	0	4	0	0
T151	2729	0	0	0
T152	845	0	0	0
T153	9489	0	0	0
T154	3716	0	0	0
T155	3073	0	0	0
T156	56862	0	0	0
T157	27982	0	0	0
T158	1944	0	0	0
T159	1093	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	1234	0	0
T70	0	5	0	0
T81	0	2	0	0
T86	0	25	0	0
T91	0	6	0	0
T138	254507	9	0	0
T141	0	1	0	0
T146	0	9	0	0
T147	0	8	0	0
T148	0	23	0	0
T149	0	11	0	0
T151	2729	0	0	0
T152	845	0	0	0
T153	9489	0	0	0
T154	3716	0	0	0
T155	3073	0	0	0
T156	56862	0	0	0
T157	27982	0	0	0
T158	1944	0	0	0
T159	1093	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	1230	0	0
T63	0	13	0	0
T70	0	3	0	0
T81	0	8	0	0
T86	0	22	0	0
T115	0	1	0	0
T138	254507	9	0	0
T141	0	5	0	0
T146	0	8	0	0
T147	0	3	0	0
T149	0	29	0	0
T151	2729	0	0	0
T152	845	0	0	0
T153	9489	0	0	0
T154	3716	0	0	0
T155	3073	0	0	0
T156	56862	0	0	0
T157	27982	0	0	0
T158	1944	0	0	0
T159	1093	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	2522	0	0
T70	0	11	0	0
T86	0	19	0	0
T91	0	10	0	0
T138	254507	12	0	0
T141	0	3	0	0
T146	0	3	0	0
T147	0	2	0	0
T148	0	21	0	0
T149	0	20	0	0
T150	0	1	0	0
T151	2729	0	0	0
T152	845	0	0	0
T153	9489	0	0	0
T154	3716	0	0	0
T155	3073	0	0	0
T156	56862	0	0	0
T157	27982	0	0	0
T158	1944	0	0	0
T159	1093	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26336342	1142	0	0
T70	0	7	0	0
T81	0	5	0	0
T86	0	18	0	0
T91	0	4	0	0
T138	254507	15	0	0
T146	0	4	0	0
T147	0	15	0	0
T148	0	17	0	0
T149	0	24	0	0
T150	0	9	0	0
T151	2729	0	0	0
T152	845	0	0	0
T153	9489	0	0	0
T154	3716	0	0	0
T155	3073	0	0	0
T156	56862	0	0	0
T157	27982	0	0	0
T158	1944	0	0	0
T159	1093	0	0	0