Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	77509950	153596	0	0
StatusRise_A	77509950	171264	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77509950	153596	0	0
T2	25764	217	0	0
T3	14940	54	0	0
T4	2436	3	0	0
T5	25398	74	0	0
T6	7695	18	0	0
T7	10524	54	0	0
T8	9366	9	0	0
T9	8691	31	0	0
T10	3594	0	0	0
T11	45273	3	0	0
T25	0	206	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77509950	171264	0	0
T1	7620	9	0	0
T2	25764	223	0	0
T3	14940	57	0	0
T4	2436	9	0	0
T5	25398	80	0	0
T6	7695	24	0	0
T7	10524	57	0	0
T8	9366	11	0	0
T9	8691	37	0	0
T10	3594	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25836650	57001	0	0
StatusRise_A	25836650	63379	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	57001	0	0
T2	8588	86	0	0
T3	4980	18	0	0
T4	812	1	0	0
T5	8466	32	0	0
T6	2565	6	0	0
T7	3508	18	0	0
T8	3122	3	0	0
T9	2897	12	0	0
T10	1198	0	0	0
T11	15091	1	0	0
T25	0	83	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	63379	0	0
T1	2540	3	0	0
T2	8588	88	0	0
T3	4980	19	0	0
T4	812	3	0	0
T5	8466	34	0	0
T6	2565	8	0	0
T7	3508	19	0	0
T8	3122	4	0	0
T9	2897	14	0	0
T10	1198	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25836650	57001	0	0
StatusRise_A	25836650	63379	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	57001	0	0
T2	8588	86	0	0
T3	4980	18	0	0
T4	812	1	0	0
T5	8466	32	0	0
T6	2565	6	0	0
T7	3508	18	0	0
T8	3122	3	0	0
T9	2897	12	0	0
T10	1198	0	0	0
T11	15091	1	0	0
T25	0	83	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	63379	0	0
T1	2540	3	0	0
T2	8588	88	0	0
T3	4980	19	0	0
T4	812	3	0	0
T5	8466	34	0	0
T6	2565	8	0	0
T7	3508	19	0	0
T8	3122	4	0	0
T9	2897	14	0	0
T10	1198	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25836650	39594	0	0
StatusRise_A	25836650	44506	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	39594	0	0
T2	8588	45	0	0
T3	4980	18	0	0
T4	812	1	0	0
T5	8466	10	0	0
T6	2565	6	0	0
T7	3508	18	0	0
T8	3122	3	0	0
T9	2897	7	0	0
T10	1198	0	0	0
T11	15091	1	0	0
T25	0	40	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	44506	0	0
T1	2540	3	0	0
T2	8588	47	0	0
T3	4980	19	0	0
T4	812	3	0	0
T5	8466	12	0	0
T6	2565	8	0	0
T7	3508	19	0	0
T8	3122	3	0	0
T9	2897	9	0	0
T10	1198	2	0	0