Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25837253	5671	0	0
EscTimeoutStoppedByClReset_A	25836650	3670909	0	0
EscTimeoutTriggersReset_A	5283046	325	0	0
RomAllowActiveState_A	25836650	62955	0	0
RomAllowCheckGoodState_A	25836650	63011	0	0
RomBlockActiveState_A	25836650	32197	0	0
RomBlockCheckGoodState_A	25836650	436798	0	0
RomIntgChkDisFalse_A	25836650	25083425	0	0
RomIntgChkDisTrue_A	25836650	205280	0	0
RstreqChkEsctimeout_A	25836650	4686	0	0
RstreqChkFsmterm_A	25836650	180	0	0
RstreqChkGlbesc_A	25836650	4686	0	0
RstreqChkMainpd_A	25836650	1053497	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25837253	5671	0	0
T11	15091	55	0	0
T13	3264	0	0	0
T14	2322	0	0	0
T16	1404	0	0	0
T25	54251	0	0	0
T37	9003	0	0	0
T38	36598	0	0	0
T42	0	57	0	0
T46	2756	0	0	0
T60	4203	0	0	0
T106	3109	0	0	0
T160	0	79	0	0
T161	0	1	0	0
T162	0	36	0	0
T163	0	142	0	0
T164	0	3	0	0
T165	0	32	0	0
T166	0	78	0	0
T167	0	55	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	3670909	0	0
T2	8588	1308	0	0
T3	4980	287	0	0
T4	812	10	0	0
T5	8466	1509	0	0
T6	2565	201	0	0
T7	3508	289	0	0
T8	3122	238	0	0
T9	2897	507	0	0
T10	1198	9	0	0
T11	15091	16	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5283046	325	0	0
T4	276	5	0	0
T5	3437	0	0	0
T6	465	0	0	0
T7	1174	0	0	0
T8	466	0	0	0
T9	1135	0	0	0
T10	383	0	0	0
T11	780	3	0	0
T12	0	2	0	0
T25	5690	0	0	0
T37	14547	0	0	0
T42	0	3	0	0
T160	0	3	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	3	0	0
T168	0	9	0	0
T169	0	9	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	62955	0	0
T1	2540	3	0	0
T2	8588	88	0	0
T3	4980	12	0	0
T4	812	3	0	0
T5	8466	34	0	0
T6	2565	8	0	0
T7	3508	12	0	0
T8	3122	4	0	0
T9	2897	14	0	0
T10	1198	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	63011	0	0
T1	2540	3	0	0
T2	8588	88	0	0
T3	4980	13	0	0
T4	812	3	0	0
T5	8466	34	0	0
T6	2565	8	0	0
T7	3508	13	0	0
T8	3122	4	0	0
T9	2897	14	0	0
T10	1198	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	32197	0	0
T6	2565	368	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	0	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T13	3263	0	0	0
T25	54250	0	0	0
T37	9002	0	0	0
T40	0	3	0	0
T52	0	17	0	0
T95	0	16	0	0
T98	0	14	0	0
T102	0	177	0	0
T106	3108	0	0	0
T170	0	15	0	0
T171	0	1557	0	0
T172	0	249	0	0
T173	0	50	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	436798	0	0
T2	8588	595	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	437	0	0
T6	2565	174	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	160	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	4212	0	0
T37	0	598	0	0
T38	0	2150	0	0
T43	0	596	0	0
T47	0	1788	0	0
T67	0	4119	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	25083425	0	0
T1	2540	2295	0	0
T2	8588	2241	0	0
T3	4980	4024	0	0
T4	812	666	0	0
T5	8466	8308	0	0
T6	2565	1188	0	0
T7	3508	2529	0	0
T8	3122	3045	0	0
T9	2897	2782	0	0
T10	1198	1013	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	205280	0	0
T2	8588	6188	0	0
T3	4980	0	0	0
T4	812	0	0	0
T5	8466	0	0	0
T6	2565	1210	0	0
T7	3508	0	0	0
T8	3122	0	0	0
T9	2897	0	0	0
T10	1198	0	0	0
T11	15091	0	0	0
T25	0	1006	0	0
T37	0	35	0	0
T40	0	806	0	0
T52	0	232	0	0
T95	0	775	0	0
T98	0	329	0	0
T102	0	848	0	0
T174	0	1313	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	4686	0	0
T3	4980	7	0	0
T4	812	1	0	0
T5	8466	0	0	0
T6	2565	2	0	0
T7	3508	3	0	0
T8	3122	0	0	0
T9	2897	0	0	0
T10	1198	1	0	0
T11	15091	1	0	0
T12	0	1	0	0
T25	54250	0	0	0
T39	0	6	0	0
T43	0	2	0	0
T46	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	180	0	0
T19	39985	40	0	0
T20	0	40	0	0
T21	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	4355	0	0	0
T29	4880	0	0	0
T30	1622	0	0	0
T31	2680	0	0	0
T32	2570	0	0	0
T33	2172	0	0	0
T34	12106	0	0	0
T35	6472	0	0	0
T36	5053	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	4686	0	0
T3	4980	7	0	0
T4	812	1	0	0
T5	8466	0	0	0
T6	2565	2	0	0
T7	3508	3	0	0
T8	3122	0	0	0
T9	2897	0	0	0
T10	1198	1	0	0
T11	15091	1	0	0
T12	0	1	0	0
T25	54250	0	0	0
T39	0	6	0	0
T43	0	2	0	0
T46	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25836650	1053497	0	0
T1	2540	6	0	0
T2	8588	662	0	0
T3	4980	156	0	0
T4	812	0	0	0
T5	8466	694	0	0
T6	2565	228	0	0
T7	3508	120	0	0
T8	3122	0	0	0
T9	2897	164	0	0
T10	1198	0	0	0
T25	0	4543	0	0
T37	0	900	0	0
T38	0	3056	0	0