Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	533442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203215

1

T1

1

T2

28

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	386888	1			T1	1		T2	182		T3	21
values[0x0]	174256	1			T2	21		T3	7		T4	6
values[0x1]	175513	1			T2	41		T3	3		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	422490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

314167

1

T1

1

T2

79

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3867	1			T25	2		T54	4		T15	14
valid_sources[0x01]	3479	1			T10	1		T25	3		T15	7
valid_sources[0x02]	2434	1			T10	1		T25	4		T54	3
valid_sources[0x03]	3435	1			T3	4		T8	1		T47	1
valid_sources[0x04]	2227	1			T8	3		T10	1		T45	1
valid_sources[0x05]	5034	1			T3	1		T10	1		T46	3
valid_sources[0x06]	2435	1			T46	3		T25	5		T54	2
valid_sources[0x07]	2593	1			T10	1		T46	22		T25	4
valid_sources[0x08]	2658	1			T8	1		T25	3		T54	1
valid_sources[0x09]	4873	1			T4	1		T8	2		T25	1
valid_sources[0x0a]	2353	1			T10	1		T45	3		T25	3
valid_sources[0x0b]	2239	1			T8	2		T25	3		T54	5
valid_sources[0x0c]	3479	1			T2	3		T8	1		T46	1
valid_sources[0x0d]	4035	1			T8	1		T10	2		T46	4
valid_sources[0x0e]	2701	1			T10	1		T46	2		T25	5
valid_sources[0x0f]	2224	1			T6	1		T15	15		T42	2
valid_sources[0x10]	2711	1			T8	1		T10	1		T25	8
valid_sources[0x11]	2451	1			T8	1		T46	1		T16	2
valid_sources[0x12]	3506	1			T8	1		T54	1		T15	10
valid_sources[0x13]	4930	1			T8	1		T25	3		T15	16
valid_sources[0x14]	2438	1			T2	3		T8	1		T10	1
valid_sources[0x15]	3201	1			T2	9		T25	10		T54	1
valid_sources[0x16]	2712	1			T10	1		T16	1		T25	9
valid_sources[0x17]	2327	1			T2	2		T8	2		T10	1
valid_sources[0x18]	2635	1			T8	1		T46	1		T47	1
valid_sources[0x19]	2259	1			T4	1		T8	1		T25	2
valid_sources[0x1a]	2374	1			T25	6		T54	3		T14	1
valid_sources[0x1b]	2145	1			T3	1		T25	3		T30	1
valid_sources[0x1c]	2672	1			T2	1		T10	1		T25	6
valid_sources[0x1d]	5789	1			T8	2		T10	2		T45	2
valid_sources[0x1e]	2956	1			T8	1		T25	2		T54	1
valid_sources[0x1f]	2249	1			T8	1		T10	1		T16	5
valid_sources[0x20]	2181	1			T8	2		T10	1		T25	1
valid_sources[0x21]	2460	1			T8	1		T10	3		T25	2
valid_sources[0x22]	2625	1			T3	1		T8	1		T25	1
valid_sources[0x23]	2207	1			T2	2		T10	2		T25	2
valid_sources[0x24]	2821	1			T8	1		T25	2		T54	1
valid_sources[0x25]	2371	1			T2	18		T25	5		T54	2
valid_sources[0x26]	3686	1			T10	2		T25	1		T54	1
valid_sources[0x27]	2960	1			T8	1		T16	1		T25	6
valid_sources[0x28]	3245	1			T2	8		T8	1		T10	1
valid_sources[0x29]	2535	1			T2	35		T10	1		T25	4
valid_sources[0x2a]	2447	1			T4	1		T10	1		T46	19
valid_sources[0x2b]	2281	1			T2	1		T8	5		T25	2
valid_sources[0x2c]	3340	1			T25	2		T54	3		T15	9
valid_sources[0x2d]	2762	1			T8	1		T10	2		T47	2
valid_sources[0x2e]	2885	1			T8	1		T25	2		T15	7
valid_sources[0x2f]	2179	1			T25	11		T54	1		T14	2
valid_sources[0x30]	2170	1			T25	2		T54	4		T15	6
valid_sources[0x31]	4037	1			T8	2		T16	2		T25	4
valid_sources[0x32]	2752	1			T8	3		T10	2		T16	6
valid_sources[0x33]	2700	1			T2	3		T10	1		T16	3
valid_sources[0x34]	3739	1			T8	2		T10	1		T25	1
valid_sources[0x35]	2387	1			T8	2		T25	2		T54	1
valid_sources[0x36]	2326	1			T17	1		T25	4		T15	10
valid_sources[0x37]	2464	1			T2	3		T8	1		T10	3
valid_sources[0x38]	3348	1			T8	1		T10	1		T25	6
valid_sources[0x39]	2817	1			T3	1		T8	1		T10	1
valid_sources[0x3a]	5384	1			T8	3		T10	1		T25	2
valid_sources[0x3b]	3527	1			T10	1		T25	1		T54	2
valid_sources[0x3c]	3712	1			T8	1		T25	4		T54	2
valid_sources[0x3d]	2381	1			T10	1		T25	2		T54	2
valid_sources[0x3e]	2354	1			T2	4		T10	1		T16	1
valid_sources[0x3f]	2508	1			T8	3		T10	2		T54	1
valid_sources[0x40]	3082	1			T2	2		T10	1		T25	3
valid_sources[0x41]	2474	1			T2	2		T10	1		T25	4
valid_sources[0x42]	2541	1			T10	1		T25	5		T54	3
valid_sources[0x43]	3088	1			T3	1		T10	2		T25	3
valid_sources[0x44]	2326	1			T3	2		T10	1		T47	1
valid_sources[0x45]	3402	1			T4	1		T25	7		T54	1
valid_sources[0x46]	1990	1			T8	2		T10	1		T54	1
valid_sources[0x47]	4266	1			T10	1		T25	3		T14	1
valid_sources[0x48]	2441	1			T10	1		T45	2		T25	3
valid_sources[0x49]	2471	1			T3	1		T46	2		T25	4
valid_sources[0x4a]	2442	1			T10	1		T46	8		T25	3
valid_sources[0x4b]	2921	1			T8	1		T25	3		T54	1
valid_sources[0x4c]	4034	1			T8	1		T25	5		T54	1
valid_sources[0x4d]	2165	1			T10	1		T16	5		T25	3
valid_sources[0x4e]	10456	1			T8	1		T25	2		T54	1
valid_sources[0x4f]	2687	1			T10	1		T47	1		T25	7
valid_sources[0x50]	2721	1			T10	3		T16	2		T25	1
valid_sources[0x51]	2771	1			T3	1		T10	1		T25	6
valid_sources[0x52]	3627	1			T8	1		T25	2		T54	2
valid_sources[0x53]	2530	1			T10	1		T16	1		T25	5
valid_sources[0x54]	2401	1			T8	2		T10	1		T47	1
valid_sources[0x55]	2285	1			T8	2		T10	1		T25	3
valid_sources[0x56]	2463	1			T10	2		T25	5		T54	3
valid_sources[0x57]	3187	1			T2	2		T3	1		T47	1
valid_sources[0x58]	3188	1			T10	1		T25	3		T54	1
valid_sources[0x59]	2419	1			T54	2		T15	8		T29	2
valid_sources[0x5a]	3295	1			T25	4		T54	1		T15	5
valid_sources[0x5b]	2293	1			T46	4		T16	1		T25	1
valid_sources[0x5c]	2348	1			T25	4		T54	1		T15	5
valid_sources[0x5d]	2980	1			T54	1		T15	11		T42	1
valid_sources[0x5e]	2498	1			T8	1		T46	2		T25	2
valid_sources[0x5f]	2497	1			T10	2		T46	5		T25	4
valid_sources[0x60]	2390	1			T46	3		T25	5		T54	1
valid_sources[0x61]	2398	1			T25	2		T15	10		T42	1
valid_sources[0x62]	5364	1			T25	6		T54	3		T30	3
valid_sources[0x63]	3331	1			T10	1		T25	7		T54	1
valid_sources[0x64]	2382	1			T10	1		T47	1		T16	8
valid_sources[0x65]	2327	1			T8	2		T14	1		T15	10
valid_sources[0x66]	2261	1			T8	2		T25	4		T15	12
valid_sources[0x67]	3513	1			T2	9		T45	4		T25	6
valid_sources[0x68]	2340	1			T8	1		T25	6		T54	2
valid_sources[0x69]	3014	1			T8	1		T45	2		T46	7
valid_sources[0x6a]	2361	1			T25	6		T54	1		T15	5
valid_sources[0x6b]	2437	1			T8	1		T10	1		T45	2
valid_sources[0x6c]	2772	1			T8	1		T16	7		T25	2
valid_sources[0x6d]	6086	1			T10	1		T54	1		T14	1
valid_sources[0x6e]	2492	1			T8	1		T10	2		T25	4
valid_sources[0x6f]	1960	1			T10	1		T46	5		T25	7
valid_sources[0x70]	3185	1			T8	2		T25	7		T54	3
valid_sources[0x71]	2542	1			T8	1		T25	2		T30	3
valid_sources[0x72]	2522	1			T15	6		T26	1		T42	1
valid_sources[0x73]	2345	1			T8	4		T25	3		T30	3
valid_sources[0x74]	2182	1			T8	1		T25	8		T54	1
valid_sources[0x75]	2836	1			T2	1		T4	1		T25	5
valid_sources[0x76]	3905	1			T46	7		T25	1		T54	1
valid_sources[0x77]	2659	1			T8	1		T25	4		T15	7
valid_sources[0x78]	3332	1			T2	6		T8	1		T16	4
valid_sources[0x79]	2249	1			T4	1		T10	1		T54	2
valid_sources[0x7a]	2527	1			T8	2		T10	2		T16	2
valid_sources[0x7b]	2620	1			T25	3		T54	1		T15	7
valid_sources[0x7c]	2490	1			T2	1		T8	3		T25	1
valid_sources[0x7d]	2983	1			T25	3		T15	11		T29	4
valid_sources[0x7e]	2628	1			T4	2		T10	1		T25	4
valid_sources[0x7f]	3109	1			T16	6		T25	3		T54	2
valid_sources[0x80]	2247	1			T8	1		T54	3		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103338

1

T1

1

T2

16

T3

8

values[0x0]

all_enables

biggest_size

64717

1

T2

3

T3

1

T4

1

values[0x1]

all_enables

biggest_size

35160

1

T2

9

T3

1

T5

4