Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26366201	14718	0	0
intr_enable_rd_A	26366201	44267	0	0
reset_en_rd_A	26366201	1419	0	0
reset_en_regwen_rd_A	26366201	1305	0	0
wake_info_capture_dis_rd_A	26366201	1375	0	0
wakeup_en_rd_A	26366201	1684	0	0
wakeup_en_regwen_rd_A	26366201	1251	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	14718	0	0
T22	323564	6	0	0
T23	234258	32	0	0
T24	0	23	0	0
T49	100493	0	0	0
T50	15699	0	0	0
T51	2265	0	0	0
T52	0	22	0	0
T66	0	63	0	0
T67	0	17	0	0
T96	0	122	0	0
T104	2562	0	0	0
T134	0	10	0	0
T135	0	23	0	0
T136	0	42	0	0
T137	7601	0	0	0
T138	2289	0	0	0
T139	1407	0	0	0
T140	16139	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	44267	0	0
T4	1087	2	0	0
T5	2695	0	0	0
T6	1466	0	0	0
T7	22643	0	0	0
T8	13863	23	0	0
T9	7617	0	0	0
T10	9899	30	0	0
T13	1033	0	0	0
T15	0	273	0	0
T17	1129	0	0	0
T26	0	12	0	0
T42	0	49	0	0
T44	0	49	0	0
T45	1062	0	0	0
T46	0	37	0	0
T53	0	65	0	0
T88	0	14	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	1419	0	0
T24	301322	3	0	0
T52	280422	11	0	0
T66	331782	0	0	0
T67	0	15	0	0
T90	0	2	0	0
T94	5862	0	0	0
T95	1268	0	0	0
T96	522342	0	0	0
T97	62396	0	0	0
T98	2291	0	0	0
T99	2118	0	0	0
T134	0	1	0	0
T141	0	9	0	0
T142	0	10	0	0
T143	0	1	0	0
T144	0	11	0	0
T145	0	8	0	0
T146	15235	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	1305	0	0
T24	301322	19	0	0
T52	280422	13	0	0
T66	331782	0	0	0
T67	0	4	0	0
T90	0	7	0	0
T92	0	13	0	0
T94	5862	0	0	0
T95	1268	0	0	0
T96	522342	0	0	0
T97	62396	0	0	0
T98	2291	0	0	0
T99	2118	0	0	0
T141	0	11	0	0
T142	0	1	0	0
T144	0	7	0	0
T145	0	4	0	0
T146	15235	0	0	0
T147	0	4	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	1375	0	0
T24	301322	10	0	0
T52	280422	11	0	0
T66	331782	0	0	0
T67	0	18	0	0
T90	0	1	0	0
T92	0	3	0	0
T93	0	11	0	0
T94	5862	0	0	0
T95	1268	0	0	0
T96	522342	0	0	0
T97	62396	0	0	0
T98	2291	0	0	0
T99	2118	0	0	0
T141	0	7	0	0
T144	0	10	0	0
T146	15235	0	0	0
T147	0	3	0	0
T148	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	1684	0	0
T24	301322	3	0	0
T52	280422	12	0	0
T66	331782	0	0	0
T67	0	9	0	0
T90	0	3	0	0
T92	0	2	0	0
T94	5862	0	0	0
T95	1268	0	0	0
T96	522342	0	0	0
T97	62396	0	0	0
T98	2291	0	0	0
T99	2118	0	0	0
T134	0	1	0	0
T141	0	8	0	0
T142	0	1	0	0
T144	0	18	0	0
T146	15235	0	0	0
T147	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26366201	1251	0	0
T24	301322	18	0	0
T52	280422	19	0	0
T66	331782	0	0	0
T67	0	18	0	0
T90	0	6	0	0
T94	5862	0	0	0
T95	1268	0	0	0
T96	522342	0	0	0
T97	62396	0	0	0
T98	2291	0	0	0
T99	2118	0	0	0
T134	0	9	0	0
T141	0	9	0	0
T142	0	2	0	0
T146	15235	0	0	0
T147	0	7	0	0
T148	0	9	0	0
T149	0	7	0	0