Unified Coverage Report :: Module :: pwrmgr_cdc

Module : pwrmgr_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cdc	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_ack_pwrdn_sync	100.00	100.00				100.00
u_ack_pwrup_sync	100.00	100.00				100.00
u_ast_sync	100.00	100.00				100.00
u_clr_req_sync	100.00	100.00				100.00
u_ext_req_sync	100.00	100.00				100.00
u_int_fsm_invalid_sync	100.00	100.00				100.00
u_ip_clk_en_sync	100.00	100.00				100.00
u_ip_clk_status_sync	100.00	100.00				100.00
u_pwrup_chg_sync	100.00	100.00				100.00
u_req_pwrdn_sync	100.00	100.00				100.00
u_req_pwrup_sync	100.00	100.00				100.00
u_scdc_sync	100.00	100.00	100.00			100.00	100.00
u_sleeping_sync	100.00	100.00				100.00
u_slow_cdc_sync	100.00	100.00	100.00			100.00	100.00
u_slow_ext_req_sync	100.00	100.00				100.00
u_sync_flash_idle	100.00	100.00				100.00
u_sync_otp	100.00	100.00				100.00
u_sync_rom_ctrl	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_cdc

	Line No.	Total	Covered	Percent
TOTAL		31	31	100.00
ALWAYS	151	3	3	100.00
ALWAYS	161	4	4	100.00
ALWAYS	173	16	16	100.00
ALWAYS	263	3	3	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
151	1	1
152	1	1
154	1	1
161	1	1
162	1	1
163	1	1
167	1	1
			MISSING_ELSE
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
263	1	1
264	1	1
266	1	1
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
			MISSING_ELSE

---

Cond Coverage for Module : pwrmgr_cdc

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       163
 EXPRESSION (slow_ast_q2 == slow_ast_q)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T7
1	0	Covered	T5,T7,T8
1	1	Covered	T3,T5,T7

---

Branch Coverage for Module : pwrmgr_cdc

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
IF	151	2	2	100.00
IF	161	3	3	100.00
IF	173	3	3	100.00
IF	263	2	2	100.00
IF	273	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	151	if ((!rst_slow_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_slow_ni))
-2-:	163	if ((slow_ast_q2 == slow_ast_q))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	173	if ((!rst_slow_ni))
-2-:	181	if (slow_cdc_sync)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (pwrup_cause_chg)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T5,T7
0	0	Covered	T1,T2,T3