Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	77316402	151189	0	0
StatusRise_A	77316402	168553	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77316402	151189	0	0
T1	1842	3	0	0
T2	8367	9	0	0
T3	4851	6	0	0
T4	3261	4	0	0
T5	8085	15	0	0
T6	4398	0	0	0
T7	67929	213	0	0
T8	41589	34	0	0
T9	22851	33	0	0
T10	29697	22	0	0
T45	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77316402	168553	0	0
T1	1842	9	0	0
T2	8367	12	0	0
T3	4851	9	0	0
T4	3261	6	0	0
T5	8085	17	0	0
T6	4398	21	0	0
T7	67929	216	0	0
T8	41589	36	0	0
T9	22851	36	0	0
T10	29697	24	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25772134	56073	0	0
StatusRise_A	25772134	62353	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	56073	0	0
T1	614	1	0	0
T2	2789	3	0	0
T3	1617	2	0	0
T4	1087	1	0	0
T5	2695	6	0	0
T6	1466	0	0	0
T7	22643	86	0	0
T8	13863	14	0	0
T9	7617	12	0	0
T10	9899	9	0	0
T45	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	62353	0	0
T1	614	3	0	0
T2	2789	4	0	0
T3	1617	3	0	0
T4	1087	2	0	0
T5	2695	7	0	0
T6	1466	7	0	0
T7	22643	87	0	0
T8	13863	15	0	0
T9	7617	13	0	0
T10	9899	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25772134	56073	0	0
StatusRise_A	25772134	62353	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	56073	0	0
T1	614	1	0	0
T2	2789	3	0	0
T3	1617	2	0	0
T4	1087	1	0	0
T5	2695	6	0	0
T6	1466	0	0	0
T7	22643	86	0	0
T8	13863	14	0	0
T9	7617	12	0	0
T10	9899	9	0	0
T45	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	62353	0	0
T1	614	3	0	0
T2	2789	4	0	0
T3	1617	3	0	0
T4	1087	2	0	0
T5	2695	7	0	0
T6	1466	7	0	0
T7	22643	87	0	0
T8	13863	15	0	0
T9	7617	13	0	0
T10	9899	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25772134	39043	0	0
StatusRise_A	25772134	43847	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	39043	0	0
T1	614	1	0	0
T2	2789	3	0	0
T3	1617	2	0	0
T4	1087	2	0	0
T5	2695	3	0	0
T6	1466	0	0	0
T7	22643	41	0	0
T8	13863	6	0	0
T9	7617	9	0	0
T10	9899	4	0	0
T45	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	43847	0	0
T1	614	3	0	0
T2	2789	4	0	0
T3	1617	3	0	0
T4	1087	2	0	0
T5	2695	3	0	0
T6	1466	7	0	0
T7	22643	42	0	0
T8	13863	6	0	0
T9	7617	10	0	0
T10	9899	4	0	0