Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25772707	5561	0	0
EscTimeoutStoppedByClReset_A	25772134	3611290	0	0
EscTimeoutTriggersReset_A	5040629	301	0	0
RomAllowActiveState_A	25772134	61966	0	0
RomAllowCheckGoodState_A	25772134	62016	0	0
RomBlockActiveState_A	25772134	30056	0	0
RomBlockCheckGoodState_A	25772134	459806	0	0
RomIntgChkDisFalse_A	25772134	25145089	0	0
RomIntgChkDisTrue_A	25772134	87547	0	0
RstreqChkEsctimeout_A	25772134	4532	0	0
RstreqChkFsmterm_A	25772134	120	0	0
RstreqChkGlbesc_A	25772134	4532	0	0
RstreqChkMainpd_A	25772134	1095698	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772707	5561	0	0
T11	14913	24	0	0
T12	0	21	0	0
T15	77060	0	0	0
T26	1216	0	0	0
T29	6161	0	0	0
T35	0	38	0	0
T42	6594	0	0	0
T43	22452	0	0	0
T48	0	7	0	0
T50	0	271	0	0
T57	1534	0	0	0
T60	3013	0	0	0
T88	2275	0	0	0
T102	3763	0	0	0
T146	0	28	0	0
T150	0	8	0	0
T151	0	55	0	0
T152	0	56	0	0
T153	0	166	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	3611290	0	0
T1	614	10	0	0
T2	2789	43	0	0
T3	1617	12	0	0
T4	1087	34	0	0
T5	2695	475	0	0
T6	1466	60	0	0
T7	22643	5974	0	0
T8	13863	2974	0	0
T9	7617	1347	0	0
T10	9899	2196	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5040629	301	0	0
T1	421	6	0	0
T2	2462	0	0	0
T3	265	0	0	0
T4	210	0	0	0
T5	1044	0	0	0
T6	507	0	0	0
T7	6904	0	0	0
T8	1582	0	0	0
T9	1577	0	0	0
T10	1125	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T35	0	2	0	0
T48	0	3	0	0
T50	0	3	0	0
T146	0	2	0	0
T150	0	5	0	0
T151	0	3	0	0
T152	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	61966	0	0
T1	614	3	0	0
T2	2789	4	0	0
T3	1617	3	0	0
T4	1087	2	0	0
T5	2695	7	0	0
T6	1466	7	0	0
T7	22643	87	0	0
T8	13863	15	0	0
T9	7617	13	0	0
T10	9899	10	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	62016	0	0
T1	614	3	0	0
T2	2789	4	0	0
T3	1617	3	0	0
T4	1087	2	0	0
T5	2695	7	0	0
T6	1466	7	0	0
T7	22643	87	0	0
T8	13863	15	0	0
T9	7617	13	0	0
T10	9899	10	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	30056	0	0
T12	14970	0	0	0
T18	1644	0	0	0
T27	33101	0	0	0
T43	22451	14	0	0
T44	5922	0	0	0
T48	14879	0	0	0
T55	1383	0	0	0
T61	0	1398	0	0
T62	0	3	0	0
T103	3357	0	0	0
T154	0	347	0	0
T155	0	29	0	0
T156	0	239	0	0
T157	0	404	0	0
T158	0	174	0	0
T159	0	1527	0	0
T160	0	1195	0	0
T161	2361	0	0	0
T162	1506	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	459806	0	0
T7	22643	1744	0	0
T8	13863	0	0	0
T9	7617	0	0	0
T10	9899	0	0	0
T13	1033	0	0	0
T15	0	595	0	0
T16	2674	0	0	0
T17	1129	0	0	0
T22	0	4677	0	0
T25	0	2218	0	0
T27	0	2269	0	0
T30	0	115	0	0
T42	0	367	0	0
T43	0	1319	0	0
T44	0	253	0	0
T45	1062	0	0	0
T46	13270	0	0	0
T47	887	0	0	0
T137	0	414	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	25145089	0	0
T1	614	446	0	0
T2	2789	2729	0	0
T3	1617	1536	0	0
T4	1087	1035	0	0
T5	2695	2634	0	0
T6	1466	926	0	0
T7	22643	21407	0	0
T8	13863	13791	0	0
T9	7617	7551	0	0
T10	9899	9825	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	87547	0	0
T7	22643	1156	0	0
T8	13863	0	0	0
T9	7617	0	0	0
T10	9899	0	0	0
T13	1033	0	0	0
T16	2674	0	0	0
T17	1129	0	0	0
T27	0	399	0	0
T28	0	2477	0	0
T45	1062	0	0	0
T46	13270	0	0	0
T47	887	0	0	0
T61	0	1885	0	0
T62	0	214	0	0
T154	0	964	0	0
T156	0	577	0	0
T163	0	3962	0	0
T164	0	2103	0	0
T165	0	880	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	4532	0	0
T1	614	1	0	0
T2	2789	0	0	0
T3	1617	0	0	0
T4	1087	0	0	0
T5	2695	0	0	0
T6	1466	0	0	0
T7	22643	0	0	0
T8	13863	0	0	0
T9	7617	0	0	0
T10	9899	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	18	0	0
T22	0	91	0	0
T29	0	4	0	0
T48	0	1	0	0
T51	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	120	0	0
T19	8911	20	0	0
T20	0	40	0	0
T21	0	20	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	2322	0	0	0
T34	1987	0	0	0
T35	15092	0	0	0
T36	1967	0	0	0
T37	9358	0	0	0
T38	1503	0	0	0
T39	4195	0	0	0
T40	1743	0	0	0
T41	1278	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	4532	0	0
T1	614	1	0	0
T2	2789	0	0	0
T3	1617	0	0	0
T4	1087	0	0	0
T5	2695	0	0	0
T6	1466	0	0	0
T7	22643	0	0	0
T8	13863	0	0	0
T9	7617	0	0	0
T10	9899	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	18	0	0
T22	0	91	0	0
T29	0	4	0	0
T48	0	1	0	0
T51	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25772134	1095698	0	0
T6	1466	27	0	0
T7	22643	1493	0	0
T8	13863	0	0	0
T9	7617	0	0	0
T10	9899	0	0	0
T13	1033	0	0	0
T15	0	5020	0	0
T17	1129	11	0	0
T25	0	2353	0	0
T27	0	3192	0	0
T29	0	92	0	0
T30	0	87	0	0
T42	0	384	0	0
T43	0	1803	0	0
T45	1062	0	0	0
T46	13270	0	0	0
T47	887	0	0	0