Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	524238	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200220

1

T1

33

T2

35

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	378126	1			T1	94		T2	182		T3	1
values[0x0]	172971	1			T1	45		T2	31		T5	65
values[0x1]	173361	1			T1	39		T2	31		T5	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	414753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

309705

1

T1

74

T2

91

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2099	1			T1	1		T6	1		T29	6
valid_sources[0x01]	2488	1			T1	4		T10	2		T29	10
valid_sources[0x02]	2277	1			T5	2		T47	1		T29	8
valid_sources[0x03]	4670	1			T1	1		T47	1		T29	6
valid_sources[0x04]	2545	1			T29	10		T79	2		T42	1
valid_sources[0x05]	2440	1			T5	1		T45	1		T29	5
valid_sources[0x06]	2420	1			T1	1		T5	1		T29	12
valid_sources[0x07]	2610	1			T1	1		T10	2		T45	1
valid_sources[0x08]	2595	1			T8	1		T10	1		T29	14
valid_sources[0x09]	2410	1			T1	2		T5	2		T29	7
valid_sources[0x0a]	2475	1			T5	2		T8	1		T29	6
valid_sources[0x0b]	2460	1			T1	1		T2	7		T5	3
valid_sources[0x0c]	3070	1			T5	3		T29	6		T30	2
valid_sources[0x0d]	2099	1			T45	1		T29	18		T79	1
valid_sources[0x0e]	5598	1			T1	1		T29	9		T79	1
valid_sources[0x0f]	2635	1			T1	4		T8	2		T29	7
valid_sources[0x10]	3085	1			T29	5		T79	2		T43	7
valid_sources[0x11]	3492	1			T1	1		T5	1		T10	1
valid_sources[0x12]	2454	1			T1	1		T5	2		T10	1
valid_sources[0x13]	2277	1			T1	1		T29	9		T43	4
valid_sources[0x14]	2423	1			T1	1		T45	1		T29	11
valid_sources[0x15]	2361	1			T8	1		T29	6		T79	1
valid_sources[0x16]	2236	1			T5	2		T29	7		T79	2
valid_sources[0x17]	2271	1			T1	1		T5	1		T10	1
valid_sources[0x18]	2458	1			T1	1		T5	1		T29	11
valid_sources[0x19]	2394	1			T10	1		T47	1		T29	15
valid_sources[0x1a]	4623	1			T2	6		T5	3		T29	11
valid_sources[0x1b]	3141	1			T5	1		T29	3		T30	3
valid_sources[0x1c]	3496	1			T47	1		T29	9		T79	1
valid_sources[0x1d]	2494	1			T10	1		T29	3		T30	1
valid_sources[0x1e]	2213	1			T1	1		T10	1		T12	1
valid_sources[0x1f]	2244	1			T1	2		T2	1		T5	1
valid_sources[0x20]	2476	1			T2	8		T5	2		T10	1
valid_sources[0x21]	3270	1			T1	2		T5	2		T8	1
valid_sources[0x22]	2729	1			T5	1		T45	2		T29	6
valid_sources[0x23]	2452	1			T1	1		T10	1		T47	1
valid_sources[0x24]	2440	1			T1	2		T29	8		T79	1
valid_sources[0x25]	2383	1			T5	1		T29	4		T79	1
valid_sources[0x26]	2352	1			T1	2		T2	15		T5	4
valid_sources[0x27]	3871	1			T1	2		T5	1		T47	1
valid_sources[0x28]	2282	1			T5	2		T8	1		T47	1
valid_sources[0x29]	2166	1			T5	1		T29	7		T79	1
valid_sources[0x2a]	2355	1			T1	2		T2	29		T5	1
valid_sources[0x2b]	2424	1			T47	1		T29	2		T79	1
valid_sources[0x2c]	3117	1			T2	8		T5	2		T47	1
valid_sources[0x2d]	3016	1			T1	2		T10	1		T29	9
valid_sources[0x2e]	2509	1			T1	1		T5	3		T29	9
valid_sources[0x2f]	2141	1			T2	3		T10	2		T29	2
valid_sources[0x30]	2410	1			T1	1		T8	1		T46	1
valid_sources[0x31]	2618	1			T1	1		T10	1		T29	3
valid_sources[0x32]	3411	1			T10	1		T29	9		T79	3
valid_sources[0x33]	2156	1			T12	1		T29	6		T79	2
valid_sources[0x34]	2495	1			T1	2		T5	2		T8	2
valid_sources[0x35]	2540	1			T1	1		T5	1		T29	9
valid_sources[0x36]	2359	1			T1	1		T47	2		T29	2
valid_sources[0x37]	2334	1			T1	2		T29	12		T79	2
valid_sources[0x38]	2841	1			T5	1		T10	1		T29	35
valid_sources[0x39]	2390	1			T45	1		T29	8		T133	3
valid_sources[0x3a]	3455	1			T1	1		T5	3		T9	35
valid_sources[0x3b]	3672	1			T1	1		T5	1		T29	12
valid_sources[0x3c]	2363	1			T5	1		T10	3		T29	11
valid_sources[0x3d]	2231	1			T1	1		T5	4		T10	1
valid_sources[0x3e]	3860	1			T1	1		T4	1		T5	1
valid_sources[0x3f]	3331	1			T1	1		T5	1		T29	3
valid_sources[0x40]	2291	1			T47	1		T29	1		T79	2
valid_sources[0x41]	2523	1			T1	1		T2	1		T5	3
valid_sources[0x42]	2681	1			T47	1		T29	11		T79	3
valid_sources[0x43]	2226	1			T5	2		T8	1		T10	1
valid_sources[0x44]	2207	1			T29	8		T79	3		T30	3
valid_sources[0x45]	2525	1			T5	1		T29	6		T79	1
valid_sources[0x46]	2404	1			T1	2		T47	2		T29	12
valid_sources[0x47]	2628	1			T1	3		T5	3		T46	4
valid_sources[0x48]	3128	1			T29	2		T79	1		T43	3
valid_sources[0x49]	2438	1			T5	1		T29	19		T79	1
valid_sources[0x4a]	2316	1			T5	1		T47	2		T29	7
valid_sources[0x4b]	2335	1			T1	1		T5	2		T29	9
valid_sources[0x4c]	12786	1			T1	1		T2	5		T5	1
valid_sources[0x4d]	3501	1			T1	1		T5	1		T8	3
valid_sources[0x4e]	2292	1			T1	2		T5	2		T10	2
valid_sources[0x4f]	2156	1			T2	3		T5	1		T47	1
valid_sources[0x50]	2472	1			T1	2		T47	1		T29	5
valid_sources[0x51]	2358	1			T5	1		T45	1		T12	1
valid_sources[0x52]	5015	1			T5	1		T47	1		T29	5
valid_sources[0x53]	2296	1			T5	2		T10	1		T29	6
valid_sources[0x54]	2417	1			T1	1		T5	1		T29	10
valid_sources[0x55]	2462	1			T1	1		T10	1		T29	2
valid_sources[0x56]	4798	1			T1	3		T5	1		T8	2
valid_sources[0x57]	2367	1			T29	8		T79	1		T30	5
valid_sources[0x58]	2411	1			T5	1		T29	12		T79	2
valid_sources[0x59]	2397	1			T1	1		T29	3		T79	2
valid_sources[0x5a]	2721	1			T29	12		T79	1		T30	3
valid_sources[0x5b]	4133	1			T1	1		T5	1		T29	4
valid_sources[0x5c]	3641	1			T5	3		T8	1		T10	1
valid_sources[0x5d]	2354	1			T1	1		T5	1		T47	1
valid_sources[0x5e]	2528	1			T1	1		T5	1		T10	1
valid_sources[0x5f]	2381	1			T5	1		T45	1		T29	4
valid_sources[0x60]	6055	1			T1	1		T2	11		T10	1
valid_sources[0x61]	2219	1			T10	1		T29	7		T79	1
valid_sources[0x62]	5261	1			T7	196		T10	1		T45	2
valid_sources[0x63]	2290	1			T5	2		T12	2		T29	7
valid_sources[0x64]	2295	1			T5	2		T45	1		T29	4
valid_sources[0x65]	3377	1			T1	1		T29	6		T30	2
valid_sources[0x66]	4804	1			T1	1		T8	1		T29	23
valid_sources[0x67]	3058	1			T5	2		T10	1		T29	5
valid_sources[0x68]	2620	1			T1	2		T5	2		T10	1
valid_sources[0x69]	2460	1			T47	1		T29	2		T42	1
valid_sources[0x6a]	2613	1			T5	3		T47	2		T29	7
valid_sources[0x6b]	2293	1			T1	1		T47	3		T29	18
valid_sources[0x6c]	3934	1			T1	1		T5	1		T8	4
valid_sources[0x6d]	2144	1			T5	1		T29	4		T79	2
valid_sources[0x6e]	3134	1			T5	3		T29	12		T79	1
valid_sources[0x6f]	3360	1			T1	1		T45	1		T29	13
valid_sources[0x70]	2284	1			T1	2		T5	1		T10	1
valid_sources[0x71]	3867	1			T1	2		T10	3		T29	18
valid_sources[0x72]	2306	1			T5	4		T46	3		T29	9
valid_sources[0x73]	2752	1			T8	1		T12	1		T29	1
valid_sources[0x74]	2595	1			T3	1		T5	1		T8	6
valid_sources[0x75]	2286	1			T5	1		T10	2		T47	1
valid_sources[0x76]	2189	1			T29	1		T42	1		T30	4
valid_sources[0x77]	2230	1			T1	1		T5	2		T29	3
valid_sources[0x78]	4123	1			T1	1		T5	1		T45	1
valid_sources[0x79]	2994	1			T5	1		T29	8		T79	4
valid_sources[0x7a]	2271	1			T10	3		T29	2		T79	2
valid_sources[0x7b]	2254	1			T5	2		T29	4		T79	1
valid_sources[0x7c]	2165	1			T1	1		T10	1		T29	2
valid_sources[0x7d]	2851	1			T1	1		T46	2		T47	1
valid_sources[0x7e]	2379	1			T29	5		T79	1		T42	1
valid_sources[0x7f]	5137	1			T5	2		T10	1		T46	2
valid_sources[0x80]	3912	1			T1	1		T46	3		T47	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

101041

1

T1

15

T2

19

T4

1

values[0x0]

all_enables

biggest_size

64333

1

T1

14

T2

12

T5

27

values[0x1]

all_enables

biggest_size

34846

1

T1

4

T2

4

T5

9