Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T44,T29

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24457157	6429	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24457157	259561	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24457157	10170605	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24457157	259544	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24457157	6429	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24457157	259561	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24457157	10170605	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24457157	259544	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	6429	0	0
T7	2972	3	0	0
T8	2852	3	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	23	0	0
T29	0	9	0	0
T30	0	21	0	0
T43	0	17	0	0
T44	1564	4	0	0
T45	2347	1	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	17	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	259561	0	0
T7	2972	57	0	0
T8	2852	632	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	1772	0	0
T29	0	669	0	0
T30	0	606	0	0
T43	0	277	0	0
T44	1564	298	0	0
T45	2347	10	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	381	0	0
T78	0	9	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	10170605	0	0
T1	6762	4592	0	0
T2	3977	0	0	0
T3	15020	0	0	0
T4	1256	0	0	0
T5	7175	3432	0	0
T6	1301	0	0	0
T7	2972	612	0	0
T8	2852	1013	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T29	0	67463	0	0
T44	0	921	0	0
T45	0	1506	0	0
T46	0	831	0	0
T47	0	960	0	0
T79	0	3150	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	259544	0	0
T7	2972	57	0	0
T8	2852	632	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	1772	0	0
T29	0	669	0	0
T30	0	606	0	0
T43	0	277	0	0
T44	1564	298	0	0
T45	2347	10	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	381	0	0
T78	0	9	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	6429	0	0
T7	2972	3	0	0
T8	2852	3	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	23	0	0
T29	0	9	0	0
T30	0	21	0	0
T43	0	17	0	0
T44	1564	4	0	0
T45	2347	1	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	17	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	259561	0	0
T7	2972	57	0	0
T8	2852	632	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	1772	0	0
T29	0	669	0	0
T30	0	606	0	0
T43	0	277	0	0
T44	1564	298	0	0
T45	2347	10	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	381	0	0
T78	0	9	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	10170605	0	0
T1	6762	4592	0	0
T2	3977	0	0	0
T3	15020	0	0	0
T4	1256	0	0	0
T5	7175	3432	0	0
T6	1301	0	0	0
T7	2972	612	0	0
T8	2852	1013	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T29	0	67463	0	0
T44	0	921	0	0
T45	0	1506	0	0
T46	0	831	0	0
T47	0	960	0	0
T79	0	3150	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	259544	0	0
T7	2972	57	0	0
T8	2852	632	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T27	0	1772	0	0
T29	0	669	0	0
T30	0	606	0	0
T43	0	277	0	0
T44	1564	298	0	0
T45	2347	10	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	381	0	0
T78	0	9	0	0