Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24991431	14824	0	0
intr_enable_rd_A	24991431	36211	0	0
reset_en_rd_A	24991431	1419	0	0
reset_en_regwen_rd_A	24991431	1184	0	0
wake_info_capture_dis_rd_A	24991431	1172	0	0
wakeup_en_rd_A	24991431	2184	0	0
wakeup_en_regwen_rd_A	24991431	1260	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	14824	0	0
T13	236505	42	0	0
T14	136587	0	0	0
T15	1324	0	0	0
T21	0	84	0	0
T22	0	119	0	0
T52	1868	0	0	0
T62	2217	0	0	0
T80	7521	0	0	0
T81	0	9	0	0
T85	8470	0	0	0
T86	1252	0	0	0
T87	52889	0	0	0
T88	2294	0	0	0
T139	0	4	0	0
T140	0	16	0	0
T141	0	14	0	0
T142	0	20	0	0
T143	0	3	0	0
T144	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	36211	0	0
T5	7175	69	0	0
T6	1301	0	0	0
T7	2972	0	0	0
T8	2852	0	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T24	0	16	0	0
T27	0	186	0	0
T28	0	27	0	0
T29	0	515	0	0
T44	1564	0	0	0
T45	2347	2	0	0
T46	1738	0	0	0
T49	0	179	0	0
T78	0	8	0	0
T80	0	35	0	0
T145	0	167	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	1419	0	0
T53	443266	9	0	0
T56	0	37	0	0
T57	0	15	0	0
T63	0	21	0	0
T82	0	15	0	0
T89	0	15	0	0
T146	0	12	0	0
T147	0	7	0	0
T148	0	11	0	0
T149	0	6	0	0
T150	3070	0	0	0
T151	15568	0	0	0
T152	66235	0	0	0
T153	5060	0	0	0
T154	4962	0	0	0
T155	6681	0	0	0
T156	27143	0	0	0
T157	10528	0	0	0
T158	10128	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	1184	0	0
T56	0	22	0	0
T57	0	5	0	0
T63	0	22	0	0
T89	0	15	0	0
T146	0	13	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	3	0	0
T159	270983	1	0	0
T160	0	31	0	0
T161	2141	0	0	0
T162	1552	0	0	0
T163	869	0	0	0
T164	821	0	0	0
T165	2005	0	0	0
T166	7540	0	0	0
T167	137292	0	0	0
T168	955	0	0	0
T169	57058	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	1172	0	0
T56	0	18	0	0
T57	0	24	0	0
T82	0	1	0	0
T89	0	4	0	0
T141	382432	7	0	0
T146	0	18	0	0
T147	0	1	0	0
T148	0	9	0	0
T149	0	9	0	0
T159	0	4	0	0
T170	8096	0	0	0
T171	680	0	0	0
T172	5755	0	0	0
T173	3348	0	0	0
T174	1128	0	0	0
T175	1861	0	0	0
T176	33416	0	0	0
T177	2245	0	0	0
T178	4876	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	2184	0	0
T56	0	79	0	0
T57	0	12	0	0
T63	0	14	0	0
T82	124963	10	0	0
T89	0	6	0	0
T146	0	10	0	0
T148	0	10	0	0
T149	0	9	0	0
T160	0	58	0	0
T179	0	19	0	0
T180	2125	0	0	0
T181	15306	0	0	0
T182	3319	0	0	0
T183	1880	0	0	0
T184	1335	0	0	0
T185	6801	0	0	0
T186	5898	0	0	0
T187	6806	0	0	0
T188	288886	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24991431	1260	0	0
T56	0	17	0	0
T57	0	32	0	0
T63	0	12	0	0
T82	0	3	0	0
T89	0	6	0	0
T141	382432	1	0	0
T146	0	14	0	0
T147	0	5	0	0
T159	0	1	0	0
T160	0	27	0	0
T170	8096	0	0	0
T171	680	0	0	0
T172	5755	0	0	0
T173	3348	0	0	0
T174	1128	0	0	0
T175	1861	0	0	0
T176	33416	0	0	0
T177	2245	0	0	0
T178	4876	0	0	0