Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73371471	148355	0	0
StatusRise_A	73371471	165457	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73371471	148355	0	0
T1	20286	34	0	0
T2	11931	12	0	0
T3	45060	3	0	0
T4	3768	0	0	0
T5	21525	45	0	0
T6	3903	3	0	0
T7	8916	52	0	0
T8	8556	12	0	0
T9	3228	9	0	0
T10	8586	54	0	0
T44	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73371471	165457	0	0
T1	20286	36	0	0
T2	11931	15	0	0
T3	45060	6	0	0
T4	3768	9	0	0
T5	21525	48	0	0
T6	3903	9	0	0
T7	8916	54	0	0
T8	8556	15	0	0
T9	3228	12	0	0
T10	8586	60	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24457157	55150	0	0
StatusRise_A	24457157	61342	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	55150	0	0
T1	6762	13	0	0
T2	3977	4	0	0
T3	15020	1	0	0
T4	1256	0	0	0
T5	7175	18	0	0
T6	1301	1	0	0
T7	2972	21	0	0
T8	2852	4	0	0
T9	1076	3	0	0
T10	2862	18	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	61342	0	0
T1	6762	14	0	0
T2	3977	5	0	0
T3	15020	2	0	0
T4	1256	3	0	0
T5	7175	19	0	0
T6	1301	3	0	0
T7	2972	22	0	0
T8	2852	5	0	0
T9	1076	4	0	0
T10	2862	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24457157	55150	0	0
StatusRise_A	24457157	61342	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	55150	0	0
T1	6762	13	0	0
T2	3977	4	0	0
T3	15020	1	0	0
T4	1256	0	0	0
T5	7175	18	0	0
T6	1301	1	0	0
T7	2972	21	0	0
T8	2852	4	0	0
T9	1076	3	0	0
T10	2862	18	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	61342	0	0
T1	6762	14	0	0
T2	3977	5	0	0
T3	15020	2	0	0
T4	1256	3	0	0
T5	7175	19	0	0
T6	1301	3	0	0
T7	2972	22	0	0
T8	2852	5	0	0
T9	1076	4	0	0
T10	2862	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24457157	38055	0	0
StatusRise_A	24457157	42773	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	38055	0	0
T1	6762	8	0	0
T2	3977	4	0	0
T3	15020	1	0	0
T4	1256	0	0	0
T5	7175	9	0	0
T6	1301	1	0	0
T7	2972	10	0	0
T8	2852	4	0	0
T9	1076	3	0	0
T10	2862	18	0	0
T44	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	42773	0	0
T1	6762	8	0	0
T2	3977	5	0	0
T3	15020	2	0	0
T4	1256	3	0	0
T5	7175	10	0	0
T6	1301	3	0	0
T7	2972	10	0	0
T8	2852	5	0	0
T9	1076	4	0	0
T10	2862	20	0	0