Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24457783	6154	0	0
EscTimeoutStoppedByClReset_A	24457157	3418783	0	0
EscTimeoutTriggersReset_A	5127300	317	0	0
RomAllowActiveState_A	24457157	60925	0	0
RomAllowCheckGoodState_A	24457157	60975	0	0
RomBlockActiveState_A	24457157	28046	0	0
RomBlockCheckGoodState_A	24457157	427443	0	0
RomIntgChkDisFalse_A	24457157	23811454	0	0
RomIntgChkDisTrue_A	24457157	116951	0	0
RstreqChkEsctimeout_A	24457157	4223	0	0
RstreqChkFsmterm_A	24457157	120	0	0
RstreqChkGlbesc_A	24457157	4223	0	0
RstreqChkMainpd_A	24457157	973731	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457783	6154	0	0
T3	15021	53	0	0
T4	1256	0	0	0
T5	7175	0	0	0
T6	1301	0	0	0
T7	2973	0	0	0
T8	2852	0	0	0
T9	1076	0	0	0
T10	2863	0	0	0
T44	1565	0	0	0
T45	2347	0	0	0
T48	0	122	0	0
T189	0	144	0	0
T190	0	5	0	0
T191	0	271	0	0
T192	0	5	0	0
T193	0	272	0	0
T194	0	258	0	0
T195	0	26	0	0
T196	0	277	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	3418783	0	0
T1	6762	650	0	0
T2	3977	70	0	0
T3	15020	11	0	0
T4	1256	26	0	0
T5	7175	1003	0	0
T6	1301	37	0	0
T7	2972	489	0	0
T8	2852	57	0	0
T9	1076	53	0	0
T10	2862	327	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5127300	317	0	0
T3	626	3	0	0
T4	291	0	0	0
T5	2671	0	0	0
T6	228	2	0	0
T7	3021	0	0	0
T8	283	0	0	0
T9	642	0	0	0
T10	1046	0	0	0
T11	0	3	0	0
T44	543	0	0	0
T45	208	0	0	0
T48	0	3	0	0
T171	0	5	0	0
T189	0	2	0	0
T190	0	2	0	0
T191	0	3	0	0
T192	0	3	0	0
T197	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	60925	0	0
T1	6762	14	0	0
T2	3977	5	0	0
T3	15020	2	0	0
T4	1256	3	0	0
T5	7175	19	0	0
T6	1301	3	0	0
T7	2972	22	0	0
T8	2852	5	0	0
T9	1076	4	0	0
T10	2862	13	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	60975	0	0
T1	6762	14	0	0
T2	3977	5	0	0
T3	15020	2	0	0
T4	1256	3	0	0
T5	7175	19	0	0
T6	1301	3	0	0
T7	2972	22	0	0
T8	2852	5	0	0
T9	1076	4	0	0
T10	2862	14	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	28046	0	0
T11	2419	0	0	0
T25	5427	1343	0	0
T26	4628	831	0	0
T28	2785	385	0	0
T43	14910	3	0	0
T48	15453	0	0	0
T49	30702	0	0	0
T78	1067	0	0	0
T97	0	4	0	0
T133	1852	0	0	0
T198	0	1	0	0
T199	0	10	0	0
T200	0	1466	0	0
T201	0	418	0	0
T202	0	190	0	0
T203	2652	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	427443	0	0
T7	2972	252	0	0
T8	2852	0	0	0
T9	1076	0	0	0
T10	2862	0	0	0
T12	1689	0	0	0
T23	2994	0	0	0
T25	0	646	0	0
T26	0	880	0	0
T27	0	4159	0	0
T28	0	349	0	0
T29	0	206	0	0
T30	0	1757	0	0
T43	0	716	0	0
T44	1564	0	0	0
T45	2347	0	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T49	0	735	0	0
T145	0	1308	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	23811454	0	0
T1	6762	6662	0	0
T2	3977	3926	0	0
T3	15020	14934	0	0
T4	1256	1052	0	0
T5	7175	7083	0	0
T6	1301	1172	0	0
T7	2972	2896	0	0
T8	2852	2454	0	0
T9	1076	976	0	0
T10	2862	1869	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	116951	0	0
T11	2419	0	0	0
T25	5427	2367	0	0
T26	4628	334	0	0
T27	0	496	0	0
T28	2785	105	0	0
T43	14910	0	0	0
T48	15453	0	0	0
T49	30702	0	0	0
T78	1067	0	0	0
T133	1852	0	0	0
T200	0	371	0	0
T202	0	167	0	0
T203	2652	0	0	0
T204	0	1969	0	0
T205	0	451	0	0
T206	0	380	0	0
T207	0	2677	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	4223	0	0
T3	15020	1	0	0
T4	1256	2	0	0
T5	7175	0	0	0
T6	1301	1	0	0
T7	2972	0	0	0
T8	2852	0	0	0
T9	1076	1	0	0
T10	2862	5	0	0
T11	0	1	0	0
T23	0	3	0	0
T25	0	2	0	0
T29	0	12	0	0
T42	0	7	0	0
T44	1564	0	0	0
T45	2347	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	120	0	0
T18	17430	40	0	0
T19	0	20	0	0
T20	0	20	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	15399	0	0	0
T34	52610	0	0	0
T35	6481	0	0	0
T36	1172	0	0	0
T37	3194	0	0	0
T38	10952	0	0	0
T39	2460	0	0	0
T40	309355	0	0	0
T41	3349	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	4223	0	0
T3	15020	1	0	0
T4	1256	2	0	0
T5	7175	0	0	0
T6	1301	1	0	0
T7	2972	0	0	0
T8	2852	0	0	0
T9	1076	1	0	0
T10	2862	5	0	0
T11	0	1	0	0
T23	0	3	0	0
T25	0	2	0	0
T29	0	12	0	0
T42	0	7	0	0
T44	1564	0	0	0
T45	2347	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24457157	973731	0	0
T7	2972	252	0	0
T8	2852	0	0	0
T9	1076	41	0	0
T10	2862	96	0	0
T12	1689	0	0	0
T23	2994	199	0	0
T25	0	636	0	0
T29	0	2086	0	0
T30	0	2281	0	0
T42	0	95	0	0
T43	0	755	0	0
T44	1564	0	0	0
T45	2347	0	0	0
T46	1738	0	0	0
T47	3771	0	0	0
T203	0	6	0	0