Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	511867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

195211

1

T1

36

T2

201

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	366320	1			T1	73		T2	407		T3	31
values[0x0]	170302	1			T1	33		T2	219		T3	15
values[0x1]	170456	1			T1	51		T2	233		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

301830

1

T1

64

T2

341

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2591	1			T1	1		T2	3		T8	3
valid_sources[0x01]	2753	1			T1	2		T2	5		T4	2
valid_sources[0x02]	2358	1			T1	5		T2	2		T4	3
valid_sources[0x03]	4068	1			T2	3		T4	3		T6	2
valid_sources[0x04]	4155	1			T2	3		T6	6		T25	2
valid_sources[0x05]	2318	1			T2	5		T6	8		T8	3
valid_sources[0x06]	2302	1			T2	4		T25	2		T13	46
valid_sources[0x07]	3018	1			T2	2		T6	6		T8	1
valid_sources[0x08]	2703	1			T4	1		T13	51		T38	4
valid_sources[0x09]	2428	1			T1	1		T2	2		T8	4
valid_sources[0x0a]	2986	1			T1	2		T2	2		T8	1
valid_sources[0x0b]	2241	1			T2	5		T25	5		T13	38
valid_sources[0x0c]	3416	1			T1	1		T2	1		T4	1
valid_sources[0x0d]	2739	1			T2	3		T6	13		T8	1
valid_sources[0x0e]	2739	1			T2	5		T6	19		T8	1
valid_sources[0x0f]	2628	1			T1	3		T2	6		T25	14
valid_sources[0x10]	2273	1			T2	4		T8	1		T13	39
valid_sources[0x11]	2467	1			T2	1		T13	38		T38	6
valid_sources[0x12]	3886	1			T2	4		T25	4		T11	1
valid_sources[0x13]	2361	1			T2	2		T8	2		T13	36
valid_sources[0x14]	2570	1			T2	3		T4	3		T13	44
valid_sources[0x15]	2233	1			T1	2		T2	3		T25	9
valid_sources[0x16]	2756	1			T2	4		T4	1		T6	1
valid_sources[0x17]	2160	1			T2	1		T25	12		T13	42
valid_sources[0x18]	2488	1			T1	1		T2	5		T25	1
valid_sources[0x19]	4231	1			T2	1		T13	40		T37	10
valid_sources[0x1a]	3666	1			T2	2		T13	35		T38	1
valid_sources[0x1b]	2292	1			T2	2		T3	64		T6	4
valid_sources[0x1c]	2327	1			T2	4		T6	3		T25	1
valid_sources[0x1d]	2150	1			T2	3		T4	1		T6	10
valid_sources[0x1e]	2405	1			T1	4		T2	5		T6	46
valid_sources[0x1f]	2331	1			T2	2		T4	4		T7	1
valid_sources[0x20]	2175	1			T2	3		T6	1		T8	1
valid_sources[0x21]	2117	1			T2	2		T8	1		T9	1
valid_sources[0x22]	2272	1			T1	1		T2	1		T25	2
valid_sources[0x23]	2435	1			T2	4		T8	1		T13	39
valid_sources[0x24]	2130	1			T1	1		T2	2		T4	2
valid_sources[0x25]	2264	1			T2	3		T25	2		T13	41
valid_sources[0x26]	2136	1			T1	1		T2	6		T8	1
valid_sources[0x27]	5022	1			T1	1		T2	2		T25	2
valid_sources[0x28]	2315	1			T2	3		T6	5		T13	37
valid_sources[0x29]	2519	1			T2	5		T13	29		T38	2
valid_sources[0x2a]	2242	1			T2	4		T25	3		T13	44
valid_sources[0x2b]	3390	1			T1	1		T2	2		T6	14
valid_sources[0x2c]	2731	1			T6	2		T8	1		T25	3
valid_sources[0x2d]	2683	1			T1	2		T2	3		T4	1
valid_sources[0x2e]	2346	1			T1	1		T2	2		T13	42
valid_sources[0x2f]	3126	1			T2	5		T6	11		T10	77
valid_sources[0x30]	2751	1			T2	5		T4	2		T8	1
valid_sources[0x31]	2254	1			T1	3		T2	3		T25	4
valid_sources[0x32]	2180	1			T2	1		T25	3		T13	19
valid_sources[0x33]	2942	1			T1	1		T2	2		T4	2
valid_sources[0x34]	3202	1			T1	1		T2	4		T6	1
valid_sources[0x35]	2905	1			T2	4		T6	14		T8	1
valid_sources[0x36]	2627	1			T2	2		T4	1		T8	2
valid_sources[0x37]	2173	1			T2	4		T4	1		T6	9
valid_sources[0x38]	2540	1			T2	1		T8	3		T25	7
valid_sources[0x39]	2239	1			T1	1		T2	3		T13	34
valid_sources[0x3a]	2593	1			T2	5		T4	1		T8	1
valid_sources[0x3b]	2564	1			T2	4		T4	4		T25	24
valid_sources[0x3c]	2386	1			T2	3		T13	52		T37	6
valid_sources[0x3d]	2244	1			T1	1		T2	10		T8	1
valid_sources[0x3e]	4990	1			T2	2		T6	3		T8	1
valid_sources[0x3f]	2659	1			T2	6		T6	42		T13	40
valid_sources[0x40]	3493	1			T2	3		T6	4		T8	4
valid_sources[0x41]	2925	1			T2	4		T4	2		T6	14
valid_sources[0x42]	2421	1			T1	2		T2	1		T8	1
valid_sources[0x43]	2344	1			T2	1		T4	1		T6	13
valid_sources[0x44]	2676	1			T2	1		T8	1		T9	1
valid_sources[0x45]	2129	1			T2	2		T8	3		T25	8
valid_sources[0x46]	2167	1			T1	1		T2	4		T8	1
valid_sources[0x47]	2580	1			T2	3		T6	47		T8	4
valid_sources[0x48]	5205	1			T2	3		T6	5		T8	1
valid_sources[0x49]	2467	1			T2	5		T8	2		T13	42
valid_sources[0x4a]	3473	1			T1	1		T2	4		T8	1
valid_sources[0x4b]	2235	1			T2	2		T6	26		T8	1
valid_sources[0x4c]	2914	1			T2	3		T6	1		T8	3
valid_sources[0x4d]	2696	1			T2	3		T6	3		T13	33
valid_sources[0x4e]	2760	1			T2	3		T8	1		T13	47
valid_sources[0x4f]	6056	1			T2	7		T8	2		T25	1
valid_sources[0x50]	2125	1			T1	2		T2	3		T25	6
valid_sources[0x51]	2354	1			T2	1		T4	4		T8	2
valid_sources[0x52]	2244	1			T2	6		T6	3		T8	3
valid_sources[0x53]	3350	1			T2	3		T4	1		T8	3
valid_sources[0x54]	4296	1			T2	7		T13	41		T38	2
valid_sources[0x55]	3003	1			T1	1		T2	2		T8	3
valid_sources[0x56]	2244	1			T1	1		T2	6		T8	4
valid_sources[0x57]	3386	1			T1	2		T2	6		T8	2
valid_sources[0x58]	3267	1			T2	2		T9	2		T13	30
valid_sources[0x59]	2530	1			T1	1		T2	3		T25	6
valid_sources[0x5a]	2600	1			T2	1		T25	6		T13	47
valid_sources[0x5b]	4355	1			T2	2		T25	5		T13	46
valid_sources[0x5c]	2071	1			T2	3		T8	3		T25	10
valid_sources[0x5d]	3459	1			T2	5		T13	46		T38	5
valid_sources[0x5e]	2632	1			T2	1		T13	42		T38	1
valid_sources[0x5f]	4244	1			T1	1		T2	1		T8	1
valid_sources[0x60]	2598	1			T1	1		T2	3		T13	34
valid_sources[0x61]	2211	1			T1	1		T2	2		T4	1
valid_sources[0x62]	2273	1			T2	1		T25	6		T13	44
valid_sources[0x63]	2525	1			T1	1		T2	2		T4	1
valid_sources[0x64]	2360	1			T2	1		T4	2		T6	8
valid_sources[0x65]	2082	1			T4	1		T8	6		T13	34
valid_sources[0x66]	2810	1			T1	1		T13	48		T37	1
valid_sources[0x67]	2448	1			T2	2		T6	5		T25	9
valid_sources[0x68]	2344	1			T1	1		T2	5		T6	36
valid_sources[0x69]	4048	1			T2	5		T4	2		T13	52
valid_sources[0x6a]	2323	1			T2	5		T25	1		T13	47
valid_sources[0x6b]	2188	1			T1	1		T2	1		T6	23
valid_sources[0x6c]	2390	1			T2	4		T8	2		T13	39
valid_sources[0x6d]	2167	1			T1	1		T2	4		T4	1
valid_sources[0x6e]	2417	1			T2	7		T4	1		T6	1
valid_sources[0x6f]	3691	1			T1	1		T2	2		T8	4
valid_sources[0x70]	2794	1			T2	5		T6	36		T8	1
valid_sources[0x71]	3477	1			T2	3		T8	1		T13	37
valid_sources[0x72]	3723	1			T2	3		T4	2		T25	1
valid_sources[0x73]	2773	1			T2	2		T4	2		T13	29
valid_sources[0x74]	2357	1			T2	3		T8	2		T25	3
valid_sources[0x75]	2691	1			T1	3		T2	2		T8	5
valid_sources[0x76]	3060	1			T1	2		T2	8		T9	1
valid_sources[0x77]	3397	1			T2	2		T8	1		T25	1
valid_sources[0x78]	2337	1			T2	4		T4	1		T8	1
valid_sources[0x79]	2356	1			T2	4		T8	1		T25	1
valid_sources[0x7a]	2056	1			T2	2		T4	2		T25	5
valid_sources[0x7b]	2153	1			T2	4		T4	2		T6	7
valid_sources[0x7c]	2071	1			T1	1		T2	6		T25	2
valid_sources[0x7d]	2722	1			T1	2		T2	4		T9	1
valid_sources[0x7e]	2374	1			T2	5		T6	4		T8	2
valid_sources[0x7f]	2191	1			T2	4		T4	1		T8	1
valid_sources[0x80]	2399	1			T2	5		T13	37		T37	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97274

1

T1

13

T2

89

T3

13

values[0x0]

all_enables

biggest_size

63317

1

T1

16

T2

73

T3

7

values[0x1]

all_enables

biggest_size

34620

1

T1

7

T2

39

T3

6