SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34883 | 1 | T2 | 392 | T6 | 307 | T10 | 1 | ||||
others[1] | 35261 | 1 | T2 | 415 | T6 | 276 | T10 | 1 | ||||
others[2] | 35029 | 1 | T2 | 409 | T6 | 288 | T25 | 297 | ||||
others[3] | 58260 | 1 | T2 | 648 | T6 | 518 | T25 | 486 | ||||
false | 19460 | 1 | T2 | 50 | T6 | 50 | T10 | 2 | ||||
true | 29483 | 1 | T1 | 1 | T2 | 102 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35034 | 1 | T2 | 415 | T6 | 281 | T25 | 301 | ||||
others[1] | 35010 | 1 | T2 | 384 | T6 | 300 | T10 | 1 | ||||
others[2] | 35030 | 1 | T2 | 390 | T6 | 307 | T10 | 1 | ||||
others[3] | 58347 | 1 | T2 | 670 | T6 | 512 | T10 | 1 | ||||
false | 12317 | 1 | T2 | 50 | T6 | 50 | T10 | 1 | ||||
true | 22414 | 1 | T1 | 1 | T2 | 102 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 696 | 1 | T3 | 1 | T5 | 1 | T8 | 5 | ||||
others[1] | 694 | 1 | T3 | 1 | T5 | 1 | T8 | 6 | ||||
others[2] | 681 | 1 | T3 | 1 | T5 | 1 | T8 | 5 | ||||
others[3] | 1104 | 1 | T5 | 1 | T8 | 9 | T10 | 1 | ||||
false | 13489 | 1 | T1 | 1 | T2 | 2 | T3 | 21 | ||||
true | 3909 | 1 | T3 | 6 | T5 | 4 | T8 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |