Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T13

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23094878	6266	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23094878	253203	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23094878	9488421	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23094878	253218	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23094878	6266	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23094878	253203	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23094878	9488421	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23094878	253218	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	6266	0	0
T2	61349	29	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	21	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	86	0	0
T14	0	19	0	0
T25	52384	16	0	0
T37	0	25	0	0
T38	0	21	0	0
T48	0	29	0	0
T81	0	19	0	0
T82	0	26	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	253203	0	0
T2	61349	1667	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	1304	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	1330	0	0
T14	0	588	0	0
T25	52384	774	0	0
T37	0	1498	0	0
T38	0	502	0	0
T48	0	649	0	0
T81	0	281	0	0
T82	0	1998	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	9488421	0	0
T1	4873	1321	0	0
T2	61349	36537	0	0
T3	3401	0	0	0
T4	3034	1425	0	0
T5	8156	0	0	0
T6	50104	25016	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	789	0	0
T10	5970	0	0	0
T13	0	103838	0	0
T25	0	21677	0	0
T37	0	23884	0	0
T38	0	8760	0	0
T83	0	893	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	253218	0	0
T2	61349	1667	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	1304	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	1330	0	0
T14	0	588	0	0
T25	52384	774	0	0
T37	0	1498	0	0
T38	0	502	0	0
T48	0	649	0	0
T81	0	281	0	0
T82	0	1998	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	6266	0	0
T2	61349	29	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	21	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	86	0	0
T14	0	19	0	0
T25	52384	16	0	0
T37	0	25	0	0
T38	0	21	0	0
T48	0	29	0	0
T81	0	19	0	0
T82	0	26	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	253203	0	0
T2	61349	1667	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	1304	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	1330	0	0
T14	0	588	0	0
T25	52384	774	0	0
T37	0	1498	0	0
T38	0	502	0	0
T48	0	649	0	0
T81	0	281	0	0
T82	0	1998	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	9488421	0	0
T1	4873	1321	0	0
T2	61349	36537	0	0
T3	3401	0	0	0
T4	3034	1425	0	0
T5	8156	0	0	0
T6	50104	25016	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	789	0	0
T10	5970	0	0	0
T13	0	103838	0	0
T25	0	21677	0	0
T37	0	23884	0	0
T38	0	8760	0	0
T83	0	893	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	253218	0	0
T2	61349	1667	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	1304	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	1330	0	0
T14	0	588	0	0
T25	52384	774	0	0
T37	0	1498	0	0
T38	0	502	0	0
T48	0	649	0	0
T81	0	281	0	0
T82	0	1998	0	0