Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23706045	14891	0	0
intr_enable_rd_A	23706045	50495	0	0
reset_en_rd_A	23706045	1447	0	0
reset_en_regwen_rd_A	23706045	1335	0	0
wake_info_capture_dis_rd_A	23706045	1233	0	0
wakeup_en_rd_A	23706045	2248	0	0
wakeup_en_regwen_rd_A	23706045	1342	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	14891	0	0
T12	2463	0	0	0
T13	243561	3	0	0
T16	1018	0	0	0
T22	0	11	0	0
T23	0	101	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	0	0	0
T48	21151	0	0	0
T52	0	54	0	0
T53	0	32	0	0
T58	5601	0	0	0
T83	3444	0	0	0
T136	0	11	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T140	0	4	0	0
T141	3124	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	50495	0	0
T1	4873	50	0	0
T2	61349	98	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	0	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	0	0	0
T13	0	2822	0	0
T24	0	361	0	0
T25	0	130	0	0
T41	0	128	0	0
T42	0	16	0	0
T81	0	186	0	0
T83	0	32	0	0
T142	0	21	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	1447	0	0
T12	2463	0	0	0
T13	243561	1	0	0
T16	1018	0	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	0	0	0
T48	21151	0	0	0
T50	0	111	0	0
T56	0	16	0	0
T58	5601	0	0	0
T70	0	5	0	0
T73	0	13	0	0
T83	3444	0	0	0
T136	0	6	0	0
T137	0	14	0	0
T139	0	8	0	0
T141	3124	0	0	0
T143	0	9	0	0
T144	0	5	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	1335	0	0
T12	2463	0	0	0
T13	243561	8	0	0
T16	1018	0	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	0	0	0
T48	21151	0	0	0
T50	0	69	0	0
T56	0	11	0	0
T58	5601	0	0	0
T70	0	8	0	0
T73	0	13	0	0
T83	3444	0	0	0
T137	0	18	0	0
T139	0	9	0	0
T141	3124	0	0	0
T143	0	12	0	0
T145	0	2	0	0
T146	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	1233	0	0
T12	2463	0	0	0
T13	243561	8	0	0
T16	1018	0	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	0	0	0
T48	21151	0	0	0
T56	0	5	0	0
T58	5601	0	0	0
T70	0	1	0	0
T73	0	13	0	0
T83	3444	0	0	0
T137	0	14	0	0
T139	0	4	0	0
T141	3124	0	0	0
T143	0	9	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	2248	0	0
T50	0	158	0	0
T53	291669	0	0	0
T56	0	15	0	0
T57	0	3	0	0
T70	0	8	0	0
T73	0	11	0	0
T137	144496	9	0	0
T143	0	27	0	0
T144	0	5	0	0
T146	0	1	0	0
T147	0	3	0	0
T148	2392	0	0	0
T149	15218	0	0	0
T150	934	0	0	0
T151	13830	0	0	0
T152	3192	0	0	0
T153	15724	0	0	0
T154	14985	0	0	0
T155	1746	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23706045	1342	0	0
T12	2463	0	0	0
T13	243561	5	0	0
T16	1018	0	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	0	0	0
T48	21151	0	0	0
T56	0	20	0	0
T58	5601	0	0	0
T70	0	9	0	0
T73	0	11	0	0
T83	3444	0	0	0
T136	0	6	0	0
T137	0	16	0	0
T139	0	12	0	0
T141	3124	0	0	0
T143	0	17	0	0
T144	0	8	0	0
T145	0	3	0	0