Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	69284634	145036	0	0
StatusRise_A	69284634	161745	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69284634	145036	0	0
T1	14619	28	0	0
T2	184047	217	0	0
T3	10203	54	0	0
T4	9102	34	0	0
T5	24468	54	0	0
T6	150312	215	0	0
T7	44775	3	0	0
T8	10239	3	0	0
T9	3141	3	0	0
T10	17910	21	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69284634	161745	0	0
T1	14619	31	0	0
T2	184047	222	0	0
T3	10203	57	0	0
T4	9102	36	0	0
T5	24468	60	0	0
T6	150312	221	0	0
T7	44775	6	0	0
T8	10239	6	0	0
T9	3141	5	0	0
T10	17910	27	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23094878	53956	0	0
StatusRise_A	23094878	59998	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	53956	0	0
T1	4873	12	0	0
T2	61349	88	0	0
T3	3401	18	0	0
T4	3034	12	0	0
T5	8156	18	0	0
T6	50104	84	0	0
T7	14925	1	0	0
T8	3413	1	0	0
T9	1047	1	0	0
T10	5970	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	59998	0	0
T1	4873	13	0	0
T2	61349	90	0	0
T3	3401	19	0	0
T4	3034	13	0	0
T5	8156	20	0	0
T6	50104	86	0	0
T7	14925	2	0	0
T8	3413	2	0	0
T9	1047	2	0	0
T10	5970	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23094878	53957	0	0
StatusRise_A	23094878	59999	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	53957	0	0
T1	4873	12	0	0
T2	61349	88	0	0
T3	3401	18	0	0
T4	3034	12	0	0
T5	8156	18	0	0
T6	50104	84	0	0
T7	14925	1	0	0
T8	3413	1	0	0
T9	1047	1	0	0
T10	5970	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	59999	0	0
T1	4873	13	0	0
T2	61349	90	0	0
T3	3401	19	0	0
T4	3034	13	0	0
T5	8156	20	0	0
T6	50104	86	0	0
T7	14925	2	0	0
T8	3413	2	0	0
T9	1047	2	0	0
T10	5970	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23094878	37123	0	0
StatusRise_A	23094878	41748	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	37123	0	0
T1	4873	4	0	0
T2	61349	41	0	0
T3	3401	18	0	0
T4	3034	10	0	0
T5	8156	18	0	0
T6	50104	47	0	0
T7	14925	1	0	0
T8	3413	1	0	0
T9	1047	1	0	0
T10	5970	7	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	41748	0	0
T1	4873	5	0	0
T2	61349	42	0	0
T3	3401	19	0	0
T4	3034	10	0	0
T5	8156	20	0	0
T6	50104	49	0	0
T7	14925	2	0	0
T8	3413	2	0	0
T9	1047	1	0	0
T10	5970	9	0	0