Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23095476	5752	0	0
EscTimeoutStoppedByClReset_A	23094878	3135268	0	0
EscTimeoutTriggersReset_A	5449500	310	0	0
RomAllowActiveState_A	23094878	59597	0	0
RomAllowCheckGoodState_A	23094878	59647	0	0
RomBlockActiveState_A	23094878	27043	0	0
RomBlockCheckGoodState_A	23094878	438199	0	0
RomIntgChkDisFalse_A	23094878	22418697	0	0
RomIntgChkDisTrue_A	23094878	152846	0	0
RstreqChkEsctimeout_A	23094878	4204	0	0
RstreqChkFsmterm_A	23094878	160	0	0
RstreqChkGlbesc_A	23094878	4204	0	0
RstreqChkMainpd_A	23094878	952553	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23095476	5752	0	0
T7	14926	42	0	0
T8	3413	0	0	0
T9	1048	0	0	0
T10	5971	0	0	0
T11	15851	270	0	0
T12	2463	22	0	0
T13	243561	0	0	0
T25	52385	0	0	0
T36	0	9	0	0
T37	42924	0	0	0
T38	18235	0	0	0
T100	0	67	0	0
T156	0	15	0	0
T157	0	52	0	0
T158	0	129	0	0
T159	0	12	0	0
T160	0	2	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	3135268	0	0
T1	4873	787	0	0
T2	61349	9246	0	0
T3	3401	317	0	0
T4	3034	154	0	0
T5	8156	294	0	0
T6	50104	10123	0	0
T7	14925	13	0	0
T8	3413	11	0	0
T9	1047	8	0	0
T10	5970	259	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5449500	310	0	0
T7	1009	3	0	0
T8	902	0	0	0
T9	348	0	0	0
T10	448	0	0	0
T11	212	3	0	0
T12	217	2	0	0
T13	205888	0	0	0
T25	5861	0	0	0
T37	5576	0	0	0
T38	6726	0	0	0
T93	0	3	0	0
T100	0	2	0	0
T101	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	2	0	0
T161	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	59597	0	0
T1	4873	13	0	0
T2	61349	90	0	0
T3	3401	12	0	0
T4	3034	13	0	0
T5	8156	13	0	0
T6	50104	86	0	0
T7	14925	2	0	0
T8	3413	2	0	0
T9	1047	2	0	0
T10	5970	9	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	59647	0	0
T1	4873	13	0	0
T2	61349	90	0	0
T3	3401	13	0	0
T4	3034	13	0	0
T5	8156	14	0	0
T6	50104	86	0	0
T7	14925	2	0	0
T8	3413	2	0	0
T9	1047	2	0	0
T10	5970	9	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	27043	0	0
T10	5970	1455	0	0
T11	15850	0	0	0
T12	2463	0	0	0
T13	243561	0	0	0
T25	52384	0	0	0
T37	42924	0	0	0
T38	18234	0	0	0
T39	4502	1023	0	0
T42	0	1408	0	0
T48	0	7	0	0
T58	5601	0	0	0
T83	3444	0	0	0
T97	0	461	0	0
T162	0	438	0	0
T163	0	133	0	0
T164	0	456	0	0
T165	0	894	0	0
T166	0	417	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	438199	0	0
T2	61349	4123	0	0
T3	3401	0	0	0
T4	3034	0	0	0
T5	8156	0	0	0
T6	50104	4188	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	909	0	0
T13	0	3212	0	0
T14	0	847	0	0
T25	52384	4005	0	0
T37	0	3347	0	0
T38	0	1351	0	0
T39	0	633	0	0
T48	0	1140	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	22418697	0	0
T1	4873	4779	0	0
T2	61349	61214	0	0
T3	3401	2525	0	0
T4	3034	2968	0	0
T5	8156	7169	0	0
T6	50104	48879	0	0
T7	14925	14826	0	0
T8	3413	3342	0	0
T9	1047	989	0	0
T10	5970	5392	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	152846	0	0
T6	50104	1066	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	416	0	0
T11	15850	0	0	0
T12	2463	0	0	0
T13	243561	0	0	0
T25	52384	1233	0	0
T37	42924	640	0	0
T38	0	340	0	0
T39	0	366	0	0
T42	0	2483	0	0
T81	0	55	0	0
T162	0	311	0	0
T167	0	514	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	4204	0	0
T3	3401	6	0	0
T4	3034	0	0	0
T5	8156	6	0	0
T6	50104	0	0	0
T7	14925	1	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	3	0	0
T11	15850	1	0	0
T12	0	1	0	0
T13	0	93	0	0
T14	0	6	0	0
T25	52384	0	0	0
T39	0	1	0	0
T43	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	160	0	0
T19	9012	20	0	0
T20	0	40	0	0
T21	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	18320	0	0	0
T29	55692	0	0	0
T30	2557	0	0	0
T31	5546	0	0	0
T32	1036	0	0	0
T33	54382	0	0	0
T34	5824	0	0	0
T35	38354	0	0	0
T36	1216	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	4204	0	0
T3	3401	6	0	0
T4	3034	0	0	0
T5	8156	6	0	0
T6	50104	0	0	0
T7	14925	1	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	3	0	0
T11	15850	1	0	0
T12	0	1	0	0
T13	0	93	0	0
T14	0	6	0	0
T25	52384	0	0	0
T39	0	1	0	0
T43	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23094878	952553	0	0
T2	61349	5175	0	0
T3	3401	130	0	0
T4	3034	0	0	0
T5	8156	103	0	0
T6	50104	4484	0	0
T7	14925	0	0	0
T8	3413	0	0	0
T9	1047	0	0	0
T10	5970	1344	0	0
T13	0	4439	0	0
T25	52384	3155	0	0
T37	0	6221	0	0
T38	0	2044	0	0
T39	0	1593	0	0