Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_intr_cg	100.00	1	100	1	64	64
WakeupDbgCable_intr_cg	100.00	1	100	1	64	64
WakeupPin_intr_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_intr_cg	100.00	1	100	1	64	64
WakeupSysrst_intr_cg	100.00	1	100	1	64	64
WakeupUsb_intr_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45808

1

T1

109

T2

11

T3

2

auto[1]

11816

1

T1

27

T2

6

T6

115

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14405

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11814

1

T1

35

T2

6

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7794

1

T1

7

T5

1

T6

77

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1040

1

T6

4

T9

4

T24

8

auto[1]

auto[0]

auto[1]

auto[0]

4705

1

T1

17

T2

2

T6

38

auto[1]

auto[1]

auto[0]

auto[0]

1033

1

T6

14

T9

6

T24

2

auto[1]

auto[1]

auto[1]

auto[1]

5038

1

T1

10

T2

4

T6

59

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45836

1

T1

108

T2

11

T3

2

auto[1]

11788

1

T1

28

T2

6

T6

109

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14401

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11720

1

T1

40

T2

3

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7801

1

T1

7

T5

1

T6

85

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1044

1

T6

12

T9

8

T24

2

auto[1]

auto[0]

auto[1]

auto[0]

4799

1

T1

12

T2

5

T6

43

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T6

6

T9

2

T24

2

auto[1]

auto[1]

auto[1]

auto[1]

4919

1

T1

16

T2

1

T6

48

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45480

1

T1

110

T2

13

T3

2

auto[1]

12144

1

T1

26

T2

4

T6

116

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14341

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11629

1

T1

41

T2

7

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7657

1

T1

7

T5

1

T6

79

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1104

1

T6

4

T9

6

T24

2

auto[1]

auto[0]

auto[1]

auto[0]

4890

1

T1

11

T2

1

T6

38

auto[1]

auto[1]

auto[0]

auto[0]

1170

1

T6

12

T9

2

T24

4

auto[1]

auto[1]

auto[1]

auto[1]

4980

1

T1

15

T2

3

T6

62

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45830

1

T1

106

T2

15

T3

2

auto[1]

11794

1

T1

30

T2

2

T6

98

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14361

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11877

1

T1

38

T2

7

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7747

1

T1

7

T5

1

T6

75

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1084

1

T6

8

T24

8

T36

8

auto[1]

auto[0]

auto[1]

auto[0]

4642

1

T1

14

T2

1

T6

33

auto[1]

auto[1]

auto[0]

auto[0]

1080

1

T6

16

T9

2

T24

4

auto[1]

auto[1]

auto[1]

auto[1]

4988

1

T1

16

T2

1

T6

41

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45839

1

T1

108

T2

14

T3

2

auto[1]

11785

1

T1

28

T2

3

T6

108

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14379

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11859

1

T1

38

T2

7

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7735

1

T1

7

T5

1

T6

75

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1066

1

T6

4

T9

10

T24

6

auto[1]

auto[0]

auto[1]

auto[0]

4660

1

T1

14

T2

1

T6

44

auto[1]

auto[1]

auto[0]

auto[0]

1092

1

T6

16

T9

2

T24

2

auto[1]

auto[1]

auto[1]

auto[1]

4967

1

T1

14

T2

2

T6

44

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45565

1

T1

108

T2

14

T3

2

auto[1]

12059

1

T1

28

T2

3

T6

129

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43910

1

T1

92

T2

9

T3

2

auto[1]

13714

1

T1

44

T2

8

T6

138

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

72

T2

9

T3

2

auto[1]

25660

1

T1

64

T2

8

T5

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24272

1

T1

27

T2

1

T3

2

auto[1]

33352

1

T1

109

T2

16

T4

3

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

14301

1

T1

20

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

11715

1

T1

42

T2

7

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

7711

1

T1

7

T5

1

T6

77

auto[0]

auto[1]

auto[1]

auto[0]

3119

1

T1

13

T6

86

T10

4

auto[1]

auto[0]

auto[0]

auto[0]

1144

1

T6

14

T9

6

T24

4

auto[1]

auto[0]

auto[1]

auto[0]

4804

1

T1

10

T2

1

T6

43

auto[1]

auto[1]

auto[0]

auto[0]

1116

1

T6

14

T9

4

T24

2

auto[1]

auto[1]

auto[1]

auto[1]

4995

1

T1

18

T2

2

T6

58

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded