Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	489935	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

188961

1

T1

733

T2

61

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	356914	1			T1	1357		T2	99		T3	1
values[0x0]	160785	1			T1	438		T2	72		T4	12
values[0x1]	161197	1			T1	408		T2	51		T4	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	387999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

290897

1

T1

1027

T2

89

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2460	1			T1	10		T5	1		T6	38
valid_sources[0x01]	1918	1			T1	4		T6	31		T8	2
valid_sources[0x02]	3895	1			T1	3		T5	1		T6	35
valid_sources[0x03]	2100	1			T1	18		T6	22		T10	102
valid_sources[0x04]	2010	1			T1	13		T3	1		T6	27
valid_sources[0x05]	1834	1			T1	13		T6	9		T9	7
valid_sources[0x06]	2339	1			T1	7		T5	2		T6	42
valid_sources[0x07]	1967	1			T1	2		T5	1		T6	39
valid_sources[0x08]	3042	1			T1	11		T4	2		T6	30
valid_sources[0x09]	2026	1			T1	7		T6	36		T8	1
valid_sources[0x0a]	3349	1			T1	1		T5	1		T6	33
valid_sources[0x0b]	4775	1			T1	12		T5	2		T6	37
valid_sources[0x0c]	3638	1			T1	14		T6	26		T9	7
valid_sources[0x0d]	3288	1			T1	8		T6	32		T8	8
valid_sources[0x0e]	2008	1			T1	8		T5	1		T6	38
valid_sources[0x0f]	2261	1			T1	5		T5	2		T6	32
valid_sources[0x10]	2805	1			T1	5		T5	1		T6	40
valid_sources[0x11]	2952	1			T1	3		T6	41		T51	3
valid_sources[0x12]	2622	1			T1	11		T4	2		T5	1
valid_sources[0x13]	2347	1			T1	2		T5	1		T6	39
valid_sources[0x14]	2903	1			T1	10		T5	1		T6	26
valid_sources[0x15]	3180	1			T1	13		T5	1		T6	23
valid_sources[0x16]	2615	1			T1	1		T5	2		T6	37
valid_sources[0x17]	1827	1			T1	12		T5	4		T6	28
valid_sources[0x18]	2169	1			T1	5		T5	2		T6	38
valid_sources[0x19]	2230	1			T1	7		T6	30		T9	11
valid_sources[0x1a]	1947	1			T1	11		T6	33		T7	1
valid_sources[0x1b]	2528	1			T1	8		T6	25		T7	1
valid_sources[0x1c]	3239	1			T1	8		T5	2		T6	33
valid_sources[0x1d]	2011	1			T1	1		T5	1		T6	35
valid_sources[0x1e]	4156	1			T1	13		T4	1		T5	2
valid_sources[0x1f]	2153	1			T1	7		T5	2		T6	46
valid_sources[0x20]	5093	1			T1	4		T5	1		T6	36
valid_sources[0x21]	2297	1			T1	8		T5	1		T6	47
valid_sources[0x22]	3354	1			T1	15		T4	1		T5	1
valid_sources[0x23]	2871	1			T1	12		T6	33		T24	1
valid_sources[0x24]	1979	1			T1	13		T5	3		T6	36
valid_sources[0x25]	2070	1			T1	3		T6	26		T19	3
valid_sources[0x26]	2187	1			T1	15		T6	52		T51	2
valid_sources[0x27]	2078	1			T1	12		T5	1		T6	24
valid_sources[0x28]	6875	1			T1	2		T5	1		T6	47
valid_sources[0x29]	2086	1			T1	6		T6	37		T71	13
valid_sources[0x2a]	1885	1			T1	6		T4	2		T5	3
valid_sources[0x2b]	3113	1			T1	9		T4	1		T5	1
valid_sources[0x2c]	3281	1			T1	5		T6	39		T8	1
valid_sources[0x2d]	2286	1			T1	12		T6	43		T24	8
valid_sources[0x2e]	2834	1			T1	1		T5	1		T6	47
valid_sources[0x2f]	1732	1			T1	4		T4	2		T5	2
valid_sources[0x30]	3560	1			T1	6		T6	34		T8	2
valid_sources[0x31]	3381	1			T1	9		T4	1		T6	22
valid_sources[0x32]	2012	1			T1	9		T6	54		T71	12
valid_sources[0x33]	2196	1			T1	16		T5	1		T6	41
valid_sources[0x34]	1819	1			T1	14		T6	23		T9	9
valid_sources[0x35]	2990	1			T1	7		T6	43		T7	1
valid_sources[0x36]	1948	1			T1	8		T6	32		T71	3
valid_sources[0x37]	2562	1			T1	5		T5	1		T6	23
valid_sources[0x38]	2097	1			T1	5		T5	2		T6	39
valid_sources[0x39]	2311	1			T1	12		T4	6		T6	48
valid_sources[0x3a]	1767	1			T1	12		T5	3		T6	25
valid_sources[0x3b]	1792	1			T1	4		T6	32		T74	2
valid_sources[0x3c]	2026	1			T1	3		T6	44		T71	1
valid_sources[0x3d]	2370	1			T1	10		T4	1		T6	28
valid_sources[0x3e]	2069	1			T1	15		T5	2		T6	27
valid_sources[0x3f]	2034	1			T1	9		T5	2		T6	22
valid_sources[0x40]	2480	1			T1	7		T6	43		T7	1
valid_sources[0x41]	2874	1			T5	1		T6	38		T9	7
valid_sources[0x42]	7908	1			T1	10		T5	4		T6	39
valid_sources[0x43]	2228	1			T1	10		T6	25		T8	3
valid_sources[0x44]	1914	1			T1	3		T6	27		T9	20
valid_sources[0x45]	3103	1			T1	2		T5	1		T6	30
valid_sources[0x46]	3522	1			T1	4		T4	1		T6	52
valid_sources[0x47]	2824	1			T1	7		T5	1		T6	29
valid_sources[0x48]	2520	1			T1	19		T4	1		T6	36
valid_sources[0x49]	3126	1			T1	1		T4	1		T5	2
valid_sources[0x4a]	3647	1			T1	2		T5	1		T6	39
valid_sources[0x4b]	2216	1			T1	12		T4	1		T6	24
valid_sources[0x4c]	2367	1			T1	4		T6	28		T7	1
valid_sources[0x4d]	2156	1			T1	15		T5	1		T6	21
valid_sources[0x4e]	1947	1			T1	4		T5	1		T6	28
valid_sources[0x4f]	2313	1			T1	14		T6	48		T7	1
valid_sources[0x50]	1996	1			T1	19		T5	1		T6	47
valid_sources[0x51]	2255	1			T1	11		T5	1		T6	38
valid_sources[0x52]	3397	1			T1	9		T5	1		T6	28
valid_sources[0x53]	4560	1			T1	12		T4	1		T6	43
valid_sources[0x54]	2148	1			T1	7		T4	2		T5	1
valid_sources[0x55]	3530	1			T5	2		T6	22		T19	1
valid_sources[0x56]	2094	1			T1	10		T6	28		T8	2
valid_sources[0x57]	2069	1			T1	6		T4	1		T6	34
valid_sources[0x58]	2109	1			T1	6		T5	2		T6	41
valid_sources[0x59]	2913	1			T1	3		T4	1		T6	44
valid_sources[0x5a]	2528	1			T1	16		T6	26		T24	15
valid_sources[0x5b]	3864	1			T1	6		T4	1		T5	1
valid_sources[0x5c]	1913	1			T1	10		T4	1		T6	31
valid_sources[0x5d]	2236	1			T1	10		T5	1		T6	30
valid_sources[0x5e]	3250	1			T1	19		T5	2		T6	34
valid_sources[0x5f]	3377	1			T1	6		T5	1		T6	22
valid_sources[0x60]	2071	1			T1	16		T6	33		T71	1
valid_sources[0x61]	2370	1			T1	2		T5	2		T6	35
valid_sources[0x62]	1844	1			T1	3		T5	2		T6	12
valid_sources[0x63]	2008	1			T1	13		T5	1		T6	38
valid_sources[0x64]	2260	1			T1	12		T6	28		T74	1
valid_sources[0x65]	1877	1			T1	3		T4	2		T5	1
valid_sources[0x66]	1906	1			T1	7		T5	1		T6	34
valid_sources[0x67]	2296	1			T1	9		T6	40		T71	1
valid_sources[0x68]	3168	1			T1	2		T6	30		T7	1
valid_sources[0x69]	2702	1			T1	10		T6	30		T19	1
valid_sources[0x6a]	2387	1			T1	13		T6	25		T8	1
valid_sources[0x6b]	2017	1			T1	1		T6	39		T74	2
valid_sources[0x6c]	1824	1			T1	6		T5	1		T6	23
valid_sources[0x6d]	6301	1			T1	12		T5	5		T6	30
valid_sources[0x6e]	2441	1			T1	7		T6	14		T9	2
valid_sources[0x6f]	3145	1			T1	5		T5	1		T6	38
valid_sources[0x70]	2022	1			T1	2		T5	1		T6	35
valid_sources[0x71]	3627	1			T1	7		T5	1		T6	32
valid_sources[0x72]	2304	1			T1	16		T6	31		T7	1
valid_sources[0x73]	1899	1			T5	3		T6	50		T8	1
valid_sources[0x74]	2683	1			T1	6		T5	1		T6	56
valid_sources[0x75]	4424	1			T1	38		T5	4		T6	38
valid_sources[0x76]	2222	1			T1	7		T5	1		T6	23
valid_sources[0x77]	2026	1			T1	17		T5	1		T6	33
valid_sources[0x78]	3220	1			T1	7		T4	1		T5	4
valid_sources[0x79]	2125	1			T1	2		T6	38		T51	2
valid_sources[0x7a]	3556	1			T1	6		T6	26		T7	2
valid_sources[0x7b]	2993	1			T1	18		T6	42		T8	1
valid_sources[0x7c]	2233	1			T1	17		T5	1		T6	23
valid_sources[0x7d]	2259	1			T1	9		T6	43		T51	1
valid_sources[0x7e]	1919	1			T1	7		T5	1		T6	42
valid_sources[0x7f]	2373	1			T1	11		T6	31		T7	1
valid_sources[0x80]	2220	1			T1	9		T6	31		T9	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

95802

1

T1

500

T2

24

T3

1

values[0x0]

all_enables

biggest_size

60302

1

T1

144

T2

26

T4

4

values[0x1]

all_enables

biggest_size

32857

1

T1

89

T2

11

T4

3